TCL CODE WITH VHDL

[AAA]

hii

i have to study TCL SCRIPTING and i have to verify the VHDL codes, i
have learnt this lannguage but have to verify the vhdl code using TCL
SCRIPT. can any one out here please tell me how to go about. Any link
or pdf doc. that explains how to do the same.
suppose i have to verify a counter. i have to force values to teh
signal, get it on the waveform. the entire process that a testbench
does, has to be performed in TCL SCRIPT...
i hope query is well explained.

thanks
HAPPY NEW YEAR TO ALL

[Rob Dekker]

To 'verify' VHDL code, you need a tool that can do the 'verification' that you want.
TCL is a command line interface into many tools that read VHDL.
Which tool are you using ?

Rob

"AAA" <abrar_a...@yahoo.co.in> wrote in message news:1135946281.8...@g44g2000cwa.googlegroups.com...

[AAA]

hii...
i'am using modelsim PE.
you saying its a command line interface, are there any commands as such
that interfaes directly with the vhdl file, suppose the vhdl file that
has to be verified is d_ff.vhd. should i even have the testbench file
along with this or just need the d_ff.vhd file. and now to interface
the script with this ie.. with the vhdl file what should be done.
should any command be used in vsim.
how can i force values to the signals, view the wave form using the
command add wave.
can you plzz help me, as in my company i should learn this on my own,
i'am a trainee and have to get this concept clear soon. can u please
give me a example using a D Flip-Flop.

it would be great n really appreciated if you help me out..

Thanks..

thanks Rob

[AAA]

A Very "Happy New Year 2006" to you & your family !!!
May this year bring in Peace, Happiness, Prosperity & Good health !!!!

take care Rob...

[Ajeetha]

Hi AAA,
Refer to MTI's TCL commands. Quickly:

1. One can do a "force clk 1, 10, 0, 20" (Or some thing similar) to
drive a clk.
2. Do a force/deposit to D input as required.

3. All of these commands can be put in a TCL file/do file and be given
to vsim -do ..

Good Luck
Ajeetha
www.noveldv.com

[AAA]

thanks !!! will try doing it..
but, what is this MTI's TCL COMMAND????..

[Ajeetha]

Hi,
MTI - Model Tech Inc - part of Mentor Graphics now. Essentially i wan
referring you to Modelsim's documentation, TCL command section of it.

Good Luck
Ajeetha

[Andy]

Verifying vhdl using one tool's TCL command language is generally not a
good idea, since that script will only run on that tool. A proper
testbench, written in vhdl, will run on any vhdl simulator, and is
generally easier to write anyway, assuming you know vhdl.

Andy

[AAA]

yes exactly...
this is what i said.. a testbench itself will simulate and verify the
entire design.. why need a script???

set d "1"
run 200
set d "0"
run 300

this is a basic TCL script in which we carry on the stimulation. this
can be done in testbench itself. so y need script. but few other
commands like "STEP" carry on line by lione simulation that makes it
easy to verify the code. "TEST" comapres values with expected values,
and many other such commands that actually help in better verification
of the design.

so any one.. pleaseeeeeeeee help me. suppose i have a d flip-flop code
in vhd (dff.vhd). i have to verify this code using a script language.
how should i start coding in TCL. i seem to have a starting problem
here...... well.. if i get the basics right, i can proceed from here...
so please any one be helpfull and sincere tell me how to go about. what
commands are suposed to invoke the design and what actually is needed
from me being a verification engineer...

THANKS

[Ajeetha]

Hi AAA,
I'm afraid you are going in the wrong direction to learn
Verification. Originally I inferred from your post that you "had to do
this in TCL" b'cos you were asked to do so (or some other reason) - but
if the objective is to learn verification, then this direction is
wrong. Learn Testbenches, they can be made self-checking too. About
"STEP" etc. - you are confusing debug with verification, when some
thing doesn't work as expected, then you go into STEP etc. (Even then
that will be last resort as it takes lot of time).

Good Luck
Ajeetha
www.noveldv.com

P.S. My consultancy company, CVC can offer an introduction to
verification course, contact me @ gmail.com <AT> ajeetha for details -
this will be a paid one though (not FREE).

[Andy]

With vhdl, you have the ability to write a self-checking testbench that
stimulates the design, monitors the outputs, and decides if they are
correct. The best part is that if someone else runs such a testbench a
few months/years down the road, it will tell them whether the design is
correct too. So any modifications they make can still be checked to
the original specifications (plus any they want to add).

The main tool for this is vhdl's assert statement that can output
status or warnings, and even break or stop the simulation based on any
condition in the simulation. These assertions can be embedded in
particular models of the testbench, or even in the RTL code being
tested, so that they have visibility of conditions that would be very
difficult to duplicate in a script. Rather than having the limitations
of the scripting language, you have the full breadth and power of the
vhdl programming language to implement the stimulus and the
verification.

Sorry, I don't use enough commands in any simulator other than run, and
setting a few breakpoints, or selecting signals to be watched or
displayed in waveforms while I'm debugging the testbench/UUT to be able
to help you. All I'm saying is that, unless this is for an assignment
that stipulates using the simulator commands to verify the design,
you're much better off learning to do it in native vhdl. The only
reason for such an assignment is so you'll later be able to see how
much better writing self-checking testbenches is.

Try inserting some "assert false;" statements in your vhdl code (these
will always stop), then play with the condition so that it only stops
(and prints a message) if something is wrong (unexpected value, etc.).

Andy

[AAA]

hi ..
thanks for the reply.
well.. i just gave an example regarding STOP, STEP.
in TCL script one uses only run, run run. here the designer uses
testbesnch for self verification. stimulates the design and verifies
the output.
i should use the commands like force and run throughout my script. i
need not have a testbench. just have the script and vhdl file in the
same project and have few commands in TCL script to invoke the vhdl
file. m i right???

thanks

[AAA]

hii..
i have written a tsl script to verify a d flip flop. i want to use
files in tcl. any commands that take the input from a file and store in
a file plzz let me know soon...
thanks

[Andy]

No. Trust me (and others), your best option is learning vhdl
testbenches. For the equivalent of what you can do from a script, the
parts of vhdl you need to learn is pretty simple anyway.

Testbenches are the preferred way of verfiying a design.

With a test bench, you don't need a script. Just run the simulation,
and it tells you if you had any errors, and stops when it is done. If
you had errors, the assertions can stop the simulator then as well, so
you can investigate (step, check values, etc.)

In fact, for regression testing (testbench is already debugged, your
just trying to verify that minor design changes have not introduced
other errors), you can speed up the simulation by disabling all the
hooks for debugging, etc.

Andy

[AAA]

well. in my earlier verification i have used testbenches, i have used
it well to verify a design, using files, assertions, comparisons were
done using testbenches, but the comapany needs a script to be written
so i have to learn the same. using testbenches is much much simpler.
anyways. if any one has a code in tcl to use files, to use a file that
has data as inputs and to force values to it, and also to call on a
file in which expected output is stored and can i add this in a wave to
verify my result.

thanks for your post andy, its certainly appreciated.

[ALu...@web.de]

Doulos offers a nice TCL course.
Have a look at their homepage.

[AAA]

hi.
i wana know how to capture an output and store it in text file.
say for example, i have to capture the q outfut of a D flip flop. and
storre it in a text file. how do i do this using tcl script. can any 1
here tell me. how do i capture an output signal of VJDL inot a text
file in tcl and store it.
ok
thanks
BYEE

[Ajeetha]

Hi,
I wonder why you won't use Google to search and find it for yourself
- it will be much faster for yourself. Anyway here is a link:

http://cslu.cse.ogi.edu/toolkit/old/old/documentation/cslurp/wincslurp/node26.html

Now, with this and Modelsim's documentation you should be able to do
what you have asked.

Good Luck
Ajeetha
www.noveldv.com

[AAA]

well i'am a new bee in TCL scripting. well, i know how to put data in a
file, but my doubt is, how can i capture the output of a DUT using TCL
script. thats not mentioned in net..
i have to capture the output of a VHDL file and store it in a text
file.
say for example, i have to capture the output "Q" of the D FLIP-FLOP
and store this in a text file. How do i capture. i have to take the
inputs of the D F-F from a text file again which i can take it very
easily. But the output Q has to be captured, so can any one out here
help me. i'am in a fix..

i have used a F-F as an example. in general i have to capture the
output of any DUT.

thanks a lot
bye

[Ajeetha]

Hi AAA,
Sorry to be little harsh - why don't you read Modelsim
documentation? Look for file "se_cmds.pdf" under install dir (or PE
version if be the case). There is "examine" command to do exactly what
you need:

----
examine /top/bus1
Returns the value of /top/bus1.
---

Also see:
http://www.altera.com/support/examples/tcl/counter_tcl.html

HTH
Ajeetha
www.noveldv.com

[AAA]

hi ajeeta.
seriously not a bit harsh!!! well.. thanks i got the idea how to use
the "examine" command. but this does not solve the problem.
what i want is, i need to capture the output of a vhd/dut and tap it on
to a TCL variable from where i can proceed with my work.
to be frank i'am the only person in my office working on TCL SCRIPT for
verification and i have completed testing in testbenches. but the
requirement is in TCL, for which i'am doing now.
u earlier spoke about a course, is it in INDIA-BANGALORE. do let me
know.

thanks.
and yes one more thing, does VCD commands help for what i'am doing.
tc
hope to get ur response soon. and i'am stuck badly and running short of
time. please get me out of this.

[Ajeetha]

Hi AAA (BTW, is that the name you go by?),
If I understand you correctly, you have got very close to where you
want to be:

Try:

set tcl_count_output [examine /dut/count_var]

This should get the value of count_var in DUT to a TCL var of name
tcl_count_output.

You may have to wrap this inside a "when" TCL command (Modelsim
specific) to get updates regularly.

[Shameless plug-in:]

>> u earlier spoke about a course, is it in INDIA-BANGALORE. do let me
know.

Yes, it is. Indeed I'm having several verification related courses in
mind/pipeline and am looking for potential customer(s). I plan to work
on need basis - if a customer says a need for a specific course, I can
work with them and tune it for them.

If interested, feel free to contact me @ gmail.com<>ajeetha

[/End of plug-in]

Good Luck
Ajeetha
www.noveldv.com

[AAA]

thankkkks dude
problem solved.

god bless

[Sumathigokul]

Hi all...

I have two doubts.

1. My first doubt is how to write the tcl script which locates my existing .vhd file and insert new line of code in it or replaces some of the existing codes and save the modified .vhd code back to same folder or in another new folder???

2. My second doubt is if i want to modify .vhd code already existing (statement of my first doubt) using TCL command, how i can perform it? for example, to force any value at .vhd file using tcl command, am running that particular command in any of the simulation tool's command line. Similarly, if i write a tcl script to modify .vhd file, where can i run that file (i.e. using which tool) ???

Regards,
Sumathi G.