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setup and hold modelling in vhdl

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sarulanx

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Aug 6, 1999, 3:00:00 AM8/6/99
to
hi,
can somebody help me in modeling setup and holdtime of an simple
D-FF in VHDL.
i have written the folowing code for setup time
(Data_In=Input data, Thd=Hold time, Tsd=setup time)


if(rising_edge(clk)) then
assert (Data_In'last_event>=Tsd)
report"Setup violation"
severity error;
end if;

can somebody help me in modelling hold time

thanks

Stefan Doll

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Aug 7, 1999, 3:00:00 AM8/7/99
to
In article <37AB4203...@iwa.dp.intel.com>,

I think this should work:

process
begin
wait until clk'event and clk='1';
wait for tH;
assert Data_In'last_event >= tH
report "hold violation"
severity Error;
end process;


Stefan

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Share what you know. Learn what you don't.

Andreas Gieriet

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Aug 7, 1999, 3:00:00 AM8/7/99
to sarulanx
sarulanx wrote:
>
> hi,
> can somebody help me in modeling setup and holdtime of an simple
> D-FF in VHDL.
> i have written the folowing code for setup time
> (Data_In=Input data, Thd=Hold time, Tsd=setup time)
>
> if(rising_edge(clk)) then
> assert (Data_In'last_event>=Tsd)
> report"Setup violation"
> severity error;
> end if;
>
> can somebody help me in modelling hold time
>
> thanks

Try something like the following code (I sketched it from scratch,
I didn't test it!):

-- Checks setup and hold times relative to the rising edge
-- Assumptions:
-- - Tsd > 0
-- - Thd > 0
-- - Tsd, Thd < clk period
process (clk, Data_In)
variable check_Thd : time := 0 fs;
begin
if rising_edge(clk) then
assert Data_In'last_event >= Tsd report "Setup violation" severity error;
check_Thd := now + Thd;
end if;
if Data_In'event then
assert now >= check_Thd report "Hold violation" severity error;
end if;
end process;


Have a look at our BestBench tool (http://www.diagonal.ch/products.html#BestBench)
It provides several checks (http://www.diagonal.ch/bbfaq.html#bbgen4).

--

_/_/_/_/ _/_/_/ Andreas Gieriet, VP R&D
_/ _/ _/ DS Diagonal Systems
_/ _/ _/_/ phone:+41-1-905-6060
_/ _/ _/ mailto:an...@diagonal.ch
_/_/_/_/ _/_/_/ http://www.diagonal.com/

me...@mench.com

unread,
Aug 7, 1999, 3:00:00 AM8/7/99
to
On Fri, 06 Aug 1999 13:13:55 -0700, sarulanx
<saru...@iwa.dp.intel.com> wrote in article
<37AB4203...@iwa.dp.intel.com>:

> can somebody help me in modeling setup and holdtime of an simple
> D-FF in VHDL.

> i have written the folowing code for setup time (Data_In=Input
> data, Thd=Hold time, Tsd=setup time)

> if(rising_edge(clk)) then
> assert (Data_In'last_event>=Tsd)
> report"Setup violation"
> severity error;
> end if;
>
> can somebody help me in modelling hold time

if rising_edge( clk'delayed( Thd)) then
assert Data_In'last_event >= Thd
report "hold violation"
severity error;
end if;

Hope this helps,

Paul

--
Paul Menchini | me...@mench.com |"The last thing I want to do is
Cadence Design Systems | www.orcad.com | spread fear, uncertainty and
P.O. Box 71767 | 919-479-1670[v] | doubt in the users' minds."
Durham, NC 27722-1767 | 919-479-1671[f] | --Don Jones, MS's Y2K Product Mgr

doron nisenbaum

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Aug 8, 1999, 3:00:00 AM8/8/99
to
Hi.

I think, that when modeling timing and violations, the best is to use
the functions supplied by the VITAL ieee libraries.

use IEEE.VITAL_Timing.all;

and the function:

VitalSetupHoldCheck (
Violation => Tviol_D_CP_posedge,
TimingData => Tmkr_D_CP_posedge,
TestSignal => D_ipd,
TestSignalName => "D",
TestDelay => 0 ns,
RefSignal => CP_ipd,
RefSignalName => "CP",
RefDelay => 0 ns,
SetupHigh => tsetup_D_CP_posedge_posedge,
SetupLow => tsetup_D_CP_negedge_posedge,
HoldHigh => thold_D_CP_posedge_posedge,
HoldLow => thold_D_CP_negedge_posedge,
CheckEnabled =>
TO_X01(( PR_ipd ) OR ( (NOT CLN_ipd) ) ) /=
'1',
RefTransition => 'R',
HeaderMsg => InstancePath & "/dfnpb",
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => WARNING);

The syntax is very simple and can be found even in the VITAL source
code.
If there are more questions i can elaborate.

Doron

Stefan Doll wrote:

> In article <37AB4203...@iwa.dp.intel.com>,
> sarulanx <saru...@iwa.dp.intel.com> wrote:
> > hi,

> > can somebody help me in modeling setup and holdtime of an simple
> > D-FF in VHDL.
> > i have written the folowing code for setup time
> > (Data_In=Input data, Thd=Hold time, Tsd=setup time)
> >
> > if(rising_edge(clk)) then
> > assert (Data_In'last_event>=Tsd)
> > report"Setup violation"
> > severity error;
> > end if;
> >
> > can somebody help me in modelling hold time
>

> I think this should work:
>
> process
> begin
> wait until clk'event and clk='1';
> wait for tH;
> assert Data_In'last_event >= tH
> report "hold violation"
> severity Error;
> end process;
>
> Stefan
>
> Sent via Deja.com http://www.deja.com/
> Share what you know. Learn what you don't.

--

-----------------------------------------------------------------------------
Doron Nisenbaum
_/_/_/ _/_/_/_/ _/
_/ _/ _/
_/ _/_/_/ _/ Chip Express (Israel) LTD.
_/ _/ _/ P.O.Box 2401
_/_/_/ _/_/_/_/ _/_/_/_/ Advanced Technology Center
Haifa , Israel 31024
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-------------------------------- Fax: +972-4855-1122
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