Why self defined type signal cannot assign value multiple times?
fl
I am learning VHDL by exercises. I find a self defined type signal
cannot assign value more than one time, see below example please.
type symbol is ('a', 't', 'd', digit, cr, other);
signal ss : symbol;
BEGIN
ss <= 't';
ss <= 'a';
Modelsim gives the following error message:
** Error: C:/Xilinx92i/xl92work/xapp219sim/fir_testbench.vhd(41):
Nonresolved signal 'ss' has multiple sources.
It is different from the built-in types? Thanks you very much.
Dave
Because this is hardware, and not software, things happen differently
than you would expect coming form a software background. These two
assignments are essentially happening in parallel, at the same time.
So, you are trying to drive the 'ss' signal with two different values,
at the same time, which won't work.
This is not particularly due to the type being user-defined. However,
the error wouldn't show up for some pre-defined types because they are
'resolved', which means there is a mechanism to handle the results of
a single signal being driven by multiply sources. For instance, with
the std_logic type, if you were to drive it with both a '0' and '1',
the result would be the signal having the value 'X' - and hopefully
this would alert the designer that there is a problem. Either way,
resolved or not, a synthesizer would error out.
Dave
Alfonso Baz
"fl" <rxj...@gmail.com> wrote in message
news:08b60262-936c-4dda...@r36g2000vbn.googlegroups.com...
I'm just learning also and dont know anything about "self defined types"
but the message "Nonresolved signal 'ss' has multiple sources."
looks fairly straight forward in that 'ss' is driven by both 't' and 'a' at
the same time.
If this code is part of a testbench then wait for some time between
statements
If not then you need some conditional statement that will assign 't' or 'a'
but not both
Thomas Stanka
> cannot assign value more than one time, see below example please.
>
> type symbol is ('a', 't', 'd', digit, cr, other);
> signal ss : symbol;
>
> BEGIN
>
> ss <= 't';
> ss <= 'a';
This is a concurent statement, which happens at the same time, you
need to specify your expected result of ss in case of this
contradictional assignment.
In VHDL this is called a resolution function.
> It is different from the built-in types? Thanks you very much.
No, in no way. But the type std_logic has a resolution function that
specifies what should happen if you write
sig <= '0';
sig <= 'Z';
You could of course write such a function for every own type.
I guess your real intention was to have the signal set to 't' and
after a dedicated delay/condition switching to 's'.
In that case you need to learn more about concurrent statements (and
processes)
bye Thomas