How to react on both rising AND falling edge?
Martin Böhm
I'm new to VHDL. Maybe someone could help me.
I have a clock signal and I want to detect both the rising and the
falling edge. The line
IF CLK'event AND CLK='1' ... works only on the rising edge.
I am using ALTERA MAX+plus II software. If I try to type the
following
IF CLK'event AND CLK='1' THEN -- for rising edge
...
ELSIF CLK'event AND CLK='0' THEN -- for falling edge
...
ENDIF;
the compiler tells me that the timing is too complex.
What shall I do?
Thank you for your assistance!
Martin
Renaud Pacalet
Hi Martin,
You're using a synthesizer (that is a tool that converts your code
in hardware), not a true simulator. So, what your "compiler"
complains about is that it has no hardware available to implement
your double edge triggered flip-flop. Perhaps should you read again
your book about Altera FPGA architecture and then try to implement
"reasonable" structures.
Regards,
--
Renaud Pacalet, ENST / COMELEC, 46 rue Barrault 75634 Paris Cedex 13
Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 | Mel : pac...@enst.fr
Eilert Backhus
Hi Martin,
To handle both edges in vhdl you can simply write
if clk'event then
This will trigger on any event.
BUT...in general it will not synthesize.
If you want to write a design for MAX+ devices
check out the datasheet wether these devices can handle negative edges at
all.
Most devices just invert the positive clock at the clk-input of the
Flipflop.
I dont think that any CPLD or FPGA architecture can handle both edges on
the same Flipflop.
If you want to speed up your design, that's not the way to do it,
but I need to know more before I can give any further help.
Have a nice synthesis
Eilert
>>>>>>>>>>>>>>>>>> Ursprüngliche Nachricht <<<<<<<<<<<<<<<<<<
Am 12.06.01, 13:20:00, schrieb Martin Böhm <Martin...@ops.de> zum Thema
How to react on both rising AND falling edge?:
Keith R. Williams
What you want to do works in simulation, but not synthesis. Software
can do many things that aren't possible in hardware. Physical flip
flops have only one clock so you can't describe two cock events for
the same flop. You need to use two flip flops and then decide what to
do with the outputs.
----
Keith
Georg Acher
k...@btv.ibm.com (Keith R. Williams) writes:
|> What you want to do works in simulation, but not synthesis. Software
|> can do many things that aren't possible in hardware. Physical flip
|> flops have only one clock so you can't describe two cock events for
|> the same flop. You need to use two flip flops and then decide what to
|> do with the outputs.
If the designs needs to run on both edges, he also can either use a clock
doubling PLL or an asynchronous "glitch" generator. The glitch generator can be
an easy replacement for the PLL, but needs very careful analysis for the target
architecture.
--
Georg Acher, ac...@in.tum.de
http://www.in.tum.de/~acher/
"Oh no, not again !" The bowl of petunias
Øystein Svendsen
| I'm new to VHDL. Maybe someone could help me.
|
| I have a clock signal and I want to detect both the rising and the
| falling edge. The line
Others have given answers, but there's one thing that you might
consider how it works for you.
If you want to detect edges on signals other than the main clock, and
the frequency of these signals is lower than the frequency of the
master clock, you can do something like this:
process
begin
if clk'event and clock = '1' then
sig2 <= sig1;
sig1 <= signal;
end if;
end process;
Then, if you want to do something on both edges on the signal, do
something like this:
process
begin
if clk'event and clock = '1' then
if sig2 = '0' and sig1 = '1' then -- rising edge
-- do someting
elsif sig2 = '1' and sig1 = '0' then -- falling edge
-- do something else
end if;
end if;
end process;
I am quite new to VHDL myself, and it was quite a breakthrough
for me after I discovered this way of doing certain things.
--
Øystein Svendsen Web: http://www.seabed.no/
SeaBed Geophysical AS Phone: +47 7350 5028
P.O. Box 5143 Lademoen Fax: +47 7350 4681
n-7447 Trondheim, Norway Email: sven...@seabed.no
Keith R. Williams
>In article <3b260f3d...@mdnews.btv.ibm.com>,
> k...@btv.ibm.com (Keith R. Williams) writes:
>|> What you want to do works in simulation, but not synthesis. Software
>|> can do many things that aren't possible in hardware. Physical flip
>|> flops have only one clock so you can't describe two cock events for
>|> the same flop. You need to use two flip flops and then decide what to
>|> do with the outputs.
>
>If the designs needs to run on both edges, he also can either use a clock
>doubling PLL or an asynchronous "glitch" generator. The glitch generator can be
>an easy replacement for the PLL, but needs very careful analysis for the target
>architecture.
Sure, assuming clock resources and bandwidth. I suppose the best way
to do this would be to then use the doubled clock as the Ck input to
the flop and the single-frequency clock as a CE. Sorta like:
Process (Clock, Reset)
if Reset
then
-- do reset stuff
elsif rising_edge(DoubleClock)
then
if Clock = 1
then
-- do the rising edge stuff
else
-- do the falling edge stuff
end if;
end if;
I'd guess that this would be dependent on the phase/delay
relationships between Clock and DoubleClock.
----
Keith
Janos Ero
nobody wanted to build circuits with two-edge clocks, everybody accepted
that this is not possible on a simple way. Now, probably as a result of
the VHDL "process ff (clk) " definition, the question arises in every
second month again and again.
Janos Ero
iglam
to "Don't do this."
Give us some more information, because you need to find another
way to accomplish whatever it is you are trying to do.
iglam
"Martin Böhm" <Martin...@ops.de> wrote in message
news:3B25FAE0...@ops.de...
iglam
of
the same clock in the same flop to do it. We should make a FAQ for all the
students trying to do this and just forward it when it comes up. Which will
be
next week...
No, I'm not volunteering :) Maybe it should just say: Register the data in
flop A with one
edge, then register the data in flop B with the inverted clock, and then
operate on the two
bits in parallel with clock A.
As far as making a single device to do this, speaking as a cell library
designer,
I'd be hard pressed to make a good one that played nicely with other flops
which
only used one clock edge. You could use two flops and a mux, and delay
the output by the amount of skew between the clock and its inversion
instituted by the inverter. You could xor the clock with a delay line
version
of itself (edge detect it) to create an artificial clock and again delay the
output
by the xor delay amount. Either way, you sacrifice clock to out time, and
silicon
area, for what is a dubious cell function.
iglam
"Janos Ero" <Jano...@cern.ch> wrote in message
news:3B270B5B...@cern.ch...