Modeling a pullup resistor in VHDL simulation
Brian Small
signal <= 'H';
This works in that then nothing else drives signal (declared as STD_LOGIC),
it goes to a vlaue of 'H'. However, in some of my lower level behavioural
blocks, I have synthesizable models with code like:
.. IF signal = '1' THEN ...
Which fails when signal = 'H', but I want it to pass. Any suggestions on a
better way to model a pull up resistor in VHDL?
- Brian Small
Phil Hays
> When I model a pullup resistor with:
I would suggest in your synthesizable code that you use the TO_X01
function. It is part of the 1164 standard. This function will convert
an 'H' to a '1', a 'L' to a '0', and all other input values to an 'X'.
This is a valuable function.
Example:
If TO_X01(signal) = '1' Then ...
OR
signal_int <= TO_X01(signal);
If signal_int = '1' Then ...
An amusing example of why to use the TO_X01 function a lot. Suppose
signal was being latched into a flip flop and driven onto bi-directional
line:
If Rising_edge(clock) Then
reg <= signal;
End If;
If oe = '1' Then
bus <= reg;
Else
bus <= 'Z';
End If;
-- end example
In simulation, if signal was a 'Z' when the rising edge of clock
happened, then bus would be 'Z' regardless of the oe. Once real
hardware is built, bus would drive soon after oe when true. Wonder how
long this bug would take to find and correct?
OR for bullet proof code, convert your example to a case statement like:
Case signal is
when '1'|'H' =>
blah; -- this was the THEN code
when '0'|'L' =>
foobar; -- this was the ELSE code
when others =>
ASSERT always
REPORT "!signal name mumblefratz! is undefined"
SEVERITY warning;
outsignals <= 'X';
End Case;
Of course, the second would be rather more of a rewrite, and may well
cause more issues.
LAST, your resister model might be something like this:
Case r_pin Is
When '1'|'Z' =>
r_pin <= '1';
When Others =>
r_pin <= 'Z';
End Case;
When the line is floating, the first 'when' will lock up the pin to
'1'. If any driver tries to output a low, the line will first go to 'X'
and then the second 'when' will take the pin to 'Z' to allow the line to
go to '0'.
Modeling resisters isn't simple. Of the three suggestion I gave, I'd
highly suggest the first, would suggest that the second is the correct
thing to do for some cases, and I think the last is a hack job.
--
Phil Hays
"Irritatingly, science claims to set limits on what
we can do, even in principle." Carl Sagan
phil_j...@my-dejanews.com
"synthesizable models". I will assume you mean lower level synthesizable
blocks.
First, I will ask why are you trying to "model" a pull-up resistor. Explain
the application. You do not want to have an "H" in synthesizable code. At
least I don't think you do. I am not sure the synthesis tool will know what
you mean, as far as "instantiate a pull-up resistor". Pullups/Pulldowns are
typically I/O cell functions and must be done in a special way, not usually
defined in the HDL. You may need to instantiate a specific I/O cell library
component. I'm not sure. I have not done PU/PD for FPGAs, only in an ASIC and
it was done at the I/O cell level, not the HDL level.
Let me try and answer the question. Assume you have a tri-state signal
(SIGNAL) that is driven by multiple drivers and also has a pull-up resistor.
This means it can be driven high ('1'), low ('0'), or pulled-up up ('H'). If
I assume your pull-up is on the PWB, I can MODEL it using a resolution
function in the test bench as follows:
SIGNAL <= 'H' when (I_SIGNAL = 'Z') else I_SIGNAL;
I_SIGNAL is the version of the signal without the pull-up. This signal goes
to H when I_SIGNAL is tristate, else it goes to the value being driven (even
U, X).
However, I am not sure this is what you want as you want SIGNAL to be
interpreted as a '1' when not driven. Thus you may have to substitute, '1',
for 'H' in the funtion above. It may not be what you really want, buy may be
what you have to do to get the simulation to work.
What you really want is for the simulator to interpret an 'H' the same as a
'1'. Not sure how to make that happen. It would depend on the simulator.
Anyone else have a better answer...
PJ
In article <7dou44$8q8$1...@news-2.news.gte.net>,
"Brian Small" <brian....@gte.net> wrote:
> When I model a oullkup resistor with:
>
> signal <= 'H';
>
> This works in that then nothing else drives signal (declared as STD_LOGIC),
> it goes to a vlaue of 'H'. However, in some of my lower level behavioural
> blocks, I have synthesizable models with code like:
>
> .. IF signal = '1' THEN ...
>
> Which fails when signal = 'H', but I want it to pass. Any suggestions on a
> better way to model a pull up resistor in VHDL?
>
> - Brian Small
>
>
-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own
VhdlCohen
>function. It is part of the 1164 standard. This function will convert
>an 'H' to a '1', a 'L' to a '0', and all other input values to an 'X'.
>This is a valuable function.
>
>Example:
>
>If TO_X01(signal) = '1' Then ...
>
TO_X01Z function can be used in the port map.
thus:
architecture X_Tb of X is
signal S : Std_Logic;
signal S_Bus : Std_Logic_Vector(15 downto 0);
begin
S <= 'H';
S_Bus <= (others => 'H');
U1 : entity Synth_Entity -- component name VHDL'93
port map(
S_input => To_X01(S),
S_Bus_Input => TO_X01(S_Bus));
S <= '1',
'Z' after 10 ns,
'0' after 50 ns,
'Z' after 200 ns;
-----------------------------------------------------------
-- Ben Cohen, Raytheon Systems, (310) 334-7389 bco...@west.raytheon.com
-- ** "VHDL Coding Styles and Methodologies, 2nd Edition", Ben Cohen,
-- ISBN 0-7923-8474-1 Kluwer Academic Publishers, 1999
-- ** "VHDL Answers to Frequently Asked Questions, 2nd Edition",
-- Ben Cohen, ISBN 0-7923-8115-7 Kluwer Academic Publishers, 1998
-- Web page: http://members.aol.com/vhdlcohen/vhdl
me...@mench.com
> When I model a oullkup resistor with:
> signal <= 'H';
> This works in that then nothing else drives signal (declared as STD_LOGIC),
> it goes to a vlaue of 'H'. However, in some of my lower level behavioural
> blocks, I have synthesizable models with code like:
> .. IF signal = '1' THEN ...
> Which fails when signal = 'H', but I want it to pass. Any
> suggestions on a better way to model a pull up resistor in VHDL?
You're modeling the pullup correctly, using the std_logic types. What's
missing is your detection. Try:
if To_X01( signal ) = '1' then
Hope this helps,
Paul
--
Paul Menchini | me...@mench.com | "Non si vive se non il
OrCAD | www.orcad.com | tempo che si ama."
P.O. Box 71767 | 919-479-1670[v] | --Claude Adrien Helvetius
Durham, NC 27722-1767 | 919-479-1671[f] |
Micha Zeiger
signal may be either H or '1' and your IF will have the same functionality
Micha Zeiger
Icc Design
Brian Small wrote:
> When I model a oullkup resistor with:
>
> signal <= 'H';
>
> This works in that then nothing else drives signal (declared as STD_LOGIC),
> it goes to a vlaue of 'H'. However, in some of my lower level behavioural
> blocks, I have synthesizable models with code like:
>
> .. IF signal = '1' THEN ...
>
> Which fails when signal = 'H', but I want it to pass. Any suggestions on a
> better way to model a pull up resistor in VHDL?
>
> - Brian Small
Brian Small
Your third suggestion (the hack) worked best for me, since
it involved no changes to my synthesizable code. I made a couple functions
which I unclude in my PCI_Stuff package:
FUNCTION PULLUP(ppin : STD_LOGIC) RETURN STD_LOGIC IS
VARIABLE ppull : STD_LOGIC;
BEGIN
CASE (ppin) IS
WHEN '1'|'Z' => ppull := '1';
WHEN OTHERS => ppull := 'Z';
END CASE;
RETURN ppull;
END PULLUP;
FUNCTION PULLDOWN(ppin : STD_LOGIC) RETURN STD_LOGIC IS
VARIABLE ppull : STD_LOGIC;
BEGIN
CASE (ppin) IS
WHEN '0'|'Z' => ppull := '0';
WHEN OTHERS => ppull := 'Z';
END CASE;
RETURN ppull;
END PULLDOWN;
- Brian Small
Phil Hays wrote in message <37002776...@sprynet.com>...
>Brian Small wrote:
>
>> When I model a pullup resistor with:
>>
>> signal <= 'H';
>>
>> This works in that then nothing else drives signal (declared as
STD_LOGIC),
>> it goes to a vlaue of 'H'. However, in some of my lower level
behavioural
>> blocks, I have synthesizable models with code like:
>>
>> .. IF signal = '1' THEN ...
>>
>> Which fails when signal = 'H', but I want it to pass. Any suggestions on
a
>> better way to model a pull up resistor in VHDL?
>>
>
>I would suggest in your synthesizable code that you use the TO_X01
>function. It is part of the 1164 standard. This function will convert
>an 'H' to a '1', a 'L' to a '0', and all other input values to an 'X'.
>This is a valuable function.
>
>Example:
>
>If TO_X01(signal) = '1' Then ...
>