VitalGlitch
Wong
Everything is fine with my functional simulation of a state machine
using ModelSim. But once I go for Post-Layout Simulation, ModelSim
shows me the following warnings:
# ** Warning: VitalGlitch: GLITCH Detected on port Y ; Preempted
Future Value := 1 @ 200152.541 ns; Newly Scheduled Value := 0 @
200153.004 ns;
# Time: 200152317 ps Iteration: 0 Instance:
/mooredemo_tb/moore_pm/current_state_h/current_state_ns_0_and2_0
..
..
..
Generally, I would need someone to give me some pointers:
1. What is Preempted Future Value and Newly Scheduled Value ?
2. How these glitches can be removed ? Of course, I am not talking
about switching off the glitch-detect option in ModelSim.
Thanks.
Mike Treseler
Wong wrote:
> # ** Warning: VitalGlitch: GLITCH Detected on port Y ; Preempted
> Future Value := 1 @ 200152.541 ns; Newly Scheduled Value := 0 @
> 200153.004 ns;
> # Time: 200152317 ps Iteration: 0 Instance:
> /mooredemo_tb/moore_pm/current_state_h/current_state_ns_0_and2_0
> How these glitches can be removed ?
They may not have to be removed if it is an internal node
of a synchronous design.
If it is a device pin, you may need an output register.
In a synchronous design, glitches on internal combinational
nodes that do not cause a setup violation at the next
register are tolerable. For example, I might make a glitchy
ripple counter driving an output register. Glitches
on the D side would be expected, but not on the Q side.
> Of course, I am not talking
> about switching off the glitch-detect option in ModelSim.
It probably makes sense to do just that for expected glitches.
-- Mike Treseler
Wong
Thanks for the pointer. But what if I have a synchronous design or
output registers and the device pins (make it simple, let say 2 bit
bus) still glitchy ? For example, I have the following SDF :
(CELL
(CELLTYPE "OUTBUF")
(INSTANCE output_pad_0)
(DELAY
(ABSOLUTE
(PORT D (1.07:1.65:2.29) (1.07:1.65:2.25))
(IOPATH D PAD (8.80:13.20:18.29) (8.80:13.20:19.55))
)
)
)
(CELL
(CELLTYPE "OUTBUF")
(INSTANCE output_pad_1)
(DELAY
(ABSOLUTE
(PORT D (0.35:0.55:0.76) (0.35:0.55:0.75))
(IOPATH D PAD (8.80:13.20:18.29) (8.80:13.20:19.55))
)
)
)
where the instance output_pad_1 and output_pad_0 drive by 2
D-registers respectively. As shown above, for PORT D of pad_1, max
delay is 0.76/0.75 and the other one is not the same. I think this
will still introduce the glitch to the device pin, am I correct ?
Mike Treseler <mike.t...@flukenetworks.com> wrote in message news:<3EC13D24...@flukenetworks.com>...
Mike Treseler
> Hi Mike,
> Thanks for the pointer. But what if I have a synchronous design or
> output registers and the device pins (make it simple, let say 2 bit
> bus) still glitchy ?
Post your code.
-- Mike Treseler
Muzaffer Kal
>Hi Mike,
> Thanks for the pointer. But what if I have a synchronous design or
>output registers and the device pins (make it simple, let say 2 bit
>bus) still glitchy ? For example, I have the following SDF :
If you're talking about the outputs of the registers arriving at the
pins at different times, you can't avoid it completely. The best you
can do is to instantiate the output registers at known locations
(better yet, use the flops in the IOs) and make sure that the loads of
the registers are the same (mainly the IO input capacitance). In that
case, the two outputs are as balanced as they can get and the rest has
to be tolerated by receiving logic.
Muzaffer Kal
http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations
Wong
Here's the code. Its fine with the functional simulation but after
P&R, I have the problems as mentioned. Thanks.
library ieee;
use ieee.std_logic_1164.all;
entity mooredemo is
port (
output : out std_logic_vector ( 1 downto 0 );
clk, rst, input : in std_logic
);
end;
architecture arch of mooredemo is
type statetype is (S0,S1,S2,S3);
signal current_state, next_state : statetype;
begin
sequential_proc : process (rst, clk)
begin
if rst = '0' then
current_state <= S0;
elsif clk'event and clk = '1' then
current_state <= next_state;
end if;
end process;
combinational_proc : process ( current_state, input )
begin
case current_state is
when S0 => if input = '1' then
next_state <= S1;
output <= "00";
else
next_state <= S0;
output <= "11";
end if;
when S1 => if input = '0' then
next_state <= S2;
output <= "01";
else
next_state <= S1;
output <= "00";
end if;
when S2 => if input = '1' then
next_state <= S3;
output <= "10";
else
next_state <= S2;
output <= "01";
end if;
when S3 => if input = '1' then
next_state <= S0;
output <= "11";
else
next_state <= S3;
output <= "10";
end if;
when others => next_state <= S0;
output <= "11";
end case;
end process;
end arch;
Wong
> On 13 May 2003 19:15:15 -0700, tatto...@yahoo.com (Wong) wrote:
>
> >Hi Mike,
> > Thanks for the pointer. But what if I have a synchronous design or
> >output registers and the device pins (make it simple, let say 2 bit
> >bus) still glitchy ? For example, I have the following SDF :
>
> If you're talking about the outputs of the registers arriving at the
> pins at different times, you can't avoid it completely. The best you
> can do is to instantiate the output registers at known locations
> (better yet, use the flops in the IOs) and make sure that the loads of
> the registers are the same (mainly the IO input capacitance). In that
> case, the two outputs are as balanced as they can get and the rest has
> to be tolerated by receiving logic.
I think you are talking about the IOB using Xilinx FPGAs, correct?
Since I am doing the P&R using anti-fuse FPGAs and I might not be able
to find the flops in the IOs except the loading(capacitance) of the
'output buffers'. Anyhow, thanks Muzaffer.
Mike Treseler
> Here's the code. Its fine with the functional simulation but after
> P&R, I have the problems as mentioned. Thanks.
The glitches are coming from your combinational outputs.
Consider getting rid of next_state and the combinational process.
and putting all the code into a single case of current_state
in the synchronous process elsif clause.
That would give you synchronous outputs by default.
-- Mike Treseler
Wong
Yes, you are right to synchronize the outputs. But its still glithcy
as the problem is not originate from this issue. It should be the P&R
delays of the primitives in the FPGA. I think I needs tech support
from the FPGA vendor. Thanks Mike.
Mike Treseler <mike.t...@flukenetworks.com> wrote in message news:<3EC3D03...@flukenetworks.com>...
Ray Andraka
your flip-flops. To fix that, change your design so that all outputs come directly from a flip-flop with no
combinatorial gating after the flip-flop.
Wong wrote:
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email r...@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759