Interface to Modelsim Simulator
Christian Plessl
I'm looking of a way to control the Modelsim VHDL/Verilog simulator 'vsim'
from a C application.
What I like to do is to start and restart a simulation, run for a certain
time, set input signals to the VHDL entity and readback the outputs of the
VHDL entity. Generally, all the stuff that can be done, using the vsim
commandline interface.
Modelsim seems to have many capabilities of simulating VHDL code, where
certain components are implemented in C-code instead of VHDL. But I cannot
figure out a convenient way of controling the simulation from an other
application.
As the commandline interface of vsim supports all the commands I need, I'm
thinking about writing a wrapper, which communicates with vsim using
bi-directional pipes and feeds the commandline interface with the
respective commands (run,force,examine), but somehow this is quite a hack.
Does anybody know of a convenient way of controling vsim from a C
application? Or from a Perl or Python application?
Thank you very much for any ideas, I appreciate it.
Chris
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Srinivasan Venkataramanan
I haven't done this sort of stuff, but just my thoughts FWIW. Why
not let Modelsim be the "Master" and let your "Application" be a slave
(provided your application has good command line interface of-course).
That way you can just use Modelsim's FLI to do similar things (again
since I haven't done that, this is just an idea). If it doesn't fit
your situation well, I see 2 options:
1.> Ask Modelsim Support
2.> Break & simplify your idea and post it in more detail here in this
NG.
Good Luck,
Srinivasan
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Srinivasan Venkataramanan
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"Christian Plessl" <ple...@REMOVE.tik.ee.ethz.ch> wrote in message
news:3c021ad1$1...@pfaff.ethz.ch...
Jonathan Bromley
<ple...@REMOVE.tik.ee.ethz.ch> writes
>Hello
>
>I'm looking of a way to control the Modelsim VHDL/Verilog simulator 'vsim'
>from a C application.
>
>What I like to do is to start and restart a simulation, run for a certain
>time, set input signals to the VHDL entity and readback the outputs of the
>VHDL entity. Generally, all the stuff that can be done, using the vsim
>commandline interface.
>Does anybody know of a convenient way of controling vsim from a C
>application? Or from a Perl or Python application?
In both Perl and Tcl it's very easy to pipe text output from the
script into a running application. I have used this to control
ModelSim. You need to remember to flush the pipe channel to get
anything to happen, because the piped output is buffered!
I don't know about Python but I guess the same is true.
Reading information back from the command-line interface is also
possible, but interpreting it and acting on it correctly might
be quite difficult in general.
I'm sure this is easy enough in C, too; but since I'm not a systems
programmer I don't have the information at my fingertips. If you
approach your systems-programmer / C-guru friends and ask them about
"piping output from a program into another application" they will
almost certainly be able to give you some help.
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Christian Plessl
> I haven't done this sort of stuff, but just my thoughts FWIW. Why
> not let Modelsim be the "Master" and let your "Application" be a slave
> (provided your application has good command line interface of-course).
> That way you can just use Modelsim's FLI to do similar things (again
> since I haven't done that, this is just an idea). If it doesn't fit
> your situation well, I see 2 options:
>
> 1.> Ask Modelsim Support
done.
> 2.> Break & simplify your idea and post it in more detail here in this
Ok, here are some more details:
What we are trying to do is a cosimulation of a CPU simulator written in
C and a application specific hardware unit written in VHDL. As the CPU
simulator is quite complex, we want to run this simulator as master and
modelsim as a slave. But I will think about this design decision again.
So some more explanations about our application:
So the idea of our co-simulation is quite easy, we would like to model the
CPU in C and sending user specific instructions to the application specific
unit coded in VHDL. For feeding the hardware unit with the respective
input, we have to send the inputs to the unit, trigger a run and
readback the results. The results will then be fed back to the CPU
simulator.
As far as I unterstand the Modelsim Foreign Language Interface (FLI) its
purpose is to create 'VHDL-like-processes' that are coded in C but run by
the scheduler of the ModelSim simulator i.e. ModelSim is the master
application.
What I am looking for is a performant way of controling the ModelSim
simulator directly be my C application.
One method of controling vsim is using the commandline interface of vsim
from the C application, but this might be quite troublesome and presumably
not very performant.
Maybe there is a more elegant way of doing this?
Chris
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Christian Plessl
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Christian Plessl
>>Does anybody know of a convenient way of controling vsim from a C
>>application? Or from a Perl or Python application?
>
> In both Perl and Tcl it's very easy to pipe text output from the
> script into a running application. I have used this to control
> ModelSim. You need to remember to flush the pipe channel to get
> anything to happen, because the piped output is buffered!
Good hint, thanks.
> Reading information back from the command-line interface is also
> possible, but interpreting it and acting on it correctly might
> be quite difficult in general.
>
> I'm sure this is easy enough in C, too; but since I'm not a systems
> programmer I don't have the information at my fingertips. If you
> approach your systems-programmer / C-guru friends and ask them about
> "piping output from a program into another application" they will
> almost certainly be able to give you some help.
Did you also have a look at alternatives of using the command line
interface? Is this the only way of scripting vsim from an other
application?
Did your application make extensive use of this kind of commuication? Did
you experience performance problems?
Best regards,
Chris
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Christian Plessl
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Steven Derrien
Christian Plessl wrote:
> Hello
>
> I'm looking of a way to control the Modelsim VHDL/Verilog simulator 'vsim'
> from a C application.
I did something very similar using synopsys VSS, using two files (to emulate
pipes)
One for input the other one for output. The goal was to co-simulate the
activity of a
processor and a FGPA board through the PCI bus.
The C program would write into on file (A) the entity input signals , which
were then read
by a VHDL testbench using textio package.
The benchmark would also save the entity output signals to the second file
(B), which was
then read by the C program.
Thanks Unix, I ran thos two programm concrretly, so everythhng was working as
if I had been using two pipes.
My main problem was to force the VHDL testbench to flush its output data into
the file
(there are no fflush like instruction in vhdl), so I had to hack a little bit
using CLI
(which i guess is the equivalent of Modelsim FLI).
Steven
Jos De Laender
Hi,
much depends of course about you want to do exactly.
But I would guess that you should examine your statement '
'control from a C application'.
If you start a process from the VHDL model, which is C implemented,
(your C application) is it then sufficiently controlled ? I think
you can use there all MTI start/stop/force etc. commands.
Just the way I would go (and went already, be it with Leapfrog)
Jos
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Marius Vollmer
> Maybe there is a more elegant way of doing this?
Whatever design you come up with, maybe you find the vhdl-posix
project useful:
http://savannah.gnu.org/projects/vhdl-posix
You probably wont find ready-to-use code there, but maybe you can use
ideas, or even better, contribute the missing parts.
What you can do currently is to read and write from arbitrary file
descriptors. So when you manage to start vsim with a pipe on some
known file descriptors, you can write a VHDL process that communicates
with the other end.
Untested code:
library gnu;
use gnu.posix.all;
piper: process
variable in_fd : integer := integer'value (getenv "INPUT_FD");
variable out_fd : integer := integer'value (getenv "OUTPUT_FD");
variable buf : string (1 to 256);
variable n : integer;
variable answer : string;
begin
loop
-- read command
read (in_fd, buf, n);
if n <= 0; then
exit;
end if;
-- act on it
answer := do_command (buf(1 to n));
-- write answer
write (out_fd, buf);
end loop;
end;