Flip-flop that trigger at both clock edges
Joseph
You might have noticed that there have been
many questions about hot to implement flip flops that
trigger at both clock edge. The following is a possible
implementation:
-- This example is not tested. There maybe typing
-- errors in it. Other suggestions & improvement
-- welcome.
library ieee; use ieee.std_logic_1164.all;
entity DFF_DEDGE is
port(
rst : in std_logic;
clk : in std_logic;
D : in std_logic;
Q : out std_logic
);
end DFF_DEDGE;
architecture puzzle of DFF_DEDGE is
signal QRISE : std_logic;
signal QFALL : std_logic;
begin
rising:process(rst, clk)
begin
if rst='1' then
QRISE <= '0';
elsif clk'event and clk='1' then
QRISE <= D;
end if;
end process rising;
falling:process(rst, clk)
begin
if rst='1' then
QFALL <='0';
elsif clk'event and clk='0' then
QFALL <= D;
end if;
end process falling;
Q <= QRISE when clk='1' else QFALL;
end puzzle;
OK! This is actually two flip flops. But this
component can do what we want - a register that
triggers at both clk edges.
Afterall, what is the different between one
flip-flop and two flip-flops? Area? Size? If this
circuit is put inside one standard cell, can we
call it one flip flip?
With the increasing use of DDR memory and more
high speed systems, we will see more and more
designs that contain registers of both rising clock
edge and falling clock edge. Is it time that we should
think about changing the existing VHDL & Verilog
standards so that the use of both clock edge is
possible?
Only if we add it to the standard, the software
will then start to support it. With current technology
the synthesiser might only be able to convert the
new syntax into two flip-flops, but maybe in a few
years time this will no longer be a issue.
There is still some other problems to solve of course.
Scan insertation is one of them. How good is the
testablilty of this "flip-flop"? Another problem is what
about synchronous reset?
By the way, should we add something about this
topic in the VHDL FAQ?
Joe
Phil Hays
> process(clk)
> if clk'event
> --double clocked logic
> end if;
end process;
> The problem is it doesn't map to hardware.
It could map into hardware and it would be a useful construct for double data
rate buses in use today.
In a sense, Virtex (and other) FPGAs support this as well. Use the DLL (or PLL
in other FPGAs) to double the clock frequency and use all one edge triggered
flipflops. From the outside world the device appears to be clocked on both
edges of the input clock. A simple program could be written that would
translate a VHDL (or Verilog?) design with dual edge FFs into a design with one
edge FFs, two clock enables and a frequency doubling PLL or DLL. I don't see
much point in doing this, however.
> So you see, there's no point in writing VHDL
> code for something you are not going to be able to map into current hardware.
That might not be true in a few years. Suppose, just for thought, that the
current trend of the logic getting faster than the interconnect continues. At
some point in time, a pipelined design with only local interconnect might be
designed that could take a clock at some frequency fx, but the fastest clock
that can be distributed over a clock tree is less than fx, maybe even fx/2 (or
even slower!). It would be then be worthwhile to have a FF that could clock on
both edges. Or even more speculative, a flipflop that could clock at a higher
multiple (4x, more??) of the clock rate using a distributed DLL structure. At
some point in the future, it might be enough of a performance gain that the
engineering costs of designing this feature into FPGAs or into ASIC libraries
makes sense.
Or suppose that power dissipation becomes much more of a problem with larger
parts running faster. As the clock tree is a major part of the power usage, the
clock tree power needs can be halved by using double edge triggered flipflops.
Joe> Only if we add it to the standard, the software
Joe> will then start to support it. With current technology
Joe> the synthesizer might only be able to convert the
Joe> new syntax into two flip-flops, but maybe in a few
Joe> years time this will no longer be a issue.
I would not vote (if I had a vote, which I don't) to add this to the language
standards today. Let the hardware technology drive the languages, the reverse
doesn't work. Next year I might give a different answer. I know less of ASICs
than of FPGAs, so an ASIC designer that wanted this feature in the languages
could change my mind rather quickly. Some restrictions apply. Your mileage
will vary.
--
Phil Hays
Ray Andraka
process(clk)
if clk'event
--double clocked logic
end if;
The problem is it doesn't map to hardware. The flip flops in PFGAs for instance
can be clocked on either the positive or negative edges, but not both for the
same flip-flop. Likewise for the majority of the flip-flops in the ASIC
libraries, as well as in CPLDs. So you see, there's no point in writing VHDL
code for something you are not going to be able to map into current hardware.
> Only if we add it to the standard, the software
> will then start to support it. With current technology
> the synthesiser might only be able to convert the
> new syntax into two flip-flops, but maybe in a few
> years time this will no longer be a issue.
>
> There is still some other problems to solve of course.
> Scan insertation is one of them. How good is the
> testablilty of this "flip-flop"? Another problem is what
> about synchronous reset?
>
> By the way, should we add something about this
> topic in the VHDL FAQ?
>
> Joe
--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email r...@andraka.com
http://www.andraka.com or http://www.fpga-guru.com
Paul Amblard
Double edge-triggered flip-flops
IEEE trans on computers, june 1981, pp 447-451