indexing arrays with enumerated types?
Kelly Hall
I'm a VHDL newbie and am having problems creating an array that is
indexed via an enumerated type I've defined earlier. Here's a tiny
sample that doesn't work:
ENTITY test IS
END test;
ARCHITECTURE behv OF test IS
TYPE enum is (ONE, TWO, THREE, FOUR, FIVE);
VARIABLE foo : ARRAY (enum) OF INTEGER;
BEGIN
foo(ONE) := 1;
END behv;
Is there a way for VHDL to do this? I don't have a very good VHDL
reference at hand: I've got "A VHDL Primer", and "The VHDL Handbook"
and the Viewlogic VHDL user guides.
Please tell me VHDL will do this: even C will do this. ;)
Kelly
--
Kelly Hall <ha...@lal.cs.byu.edu>
http://lal.cs.byu.edu/people/hall.html
Charles F. Shelor
>Hi all,
>
>I'm a VHDL newbie and am having problems creating an array that is
>indexed via an enumerated type I've defined earlier. Here's a tiny
>sample that doesn't work:
>
>ENTITY test IS
>END test;
>
>ARCHITECTURE behv OF test IS
> TYPE enum is (ONE, TWO, THREE, FOUR, FIVE);
> VARIABLE foo : ARRAY (enum) OF INTEGER;
>BEGIN
> foo(ONE) := 1;
>END behv;
>
A Few modifications are needed to correct your architecture:
A type must be declared separately from creating an object
of that type. (ie. define the array of enum). Next, variables
cannot be declared at the architecture level (ignoring VHDL-93
global variables), you need a signal. Then use a signal
assignment rather than variable assignment.
ARCHITECTURE behv OF test IS
TYPE enum is (ONE, TWO, THREE, FOUR, FIVE);
TYPE enum_array IS ARRAY (enum) OF INTEGER;
SIGNAL foo: enum_array;
BEGIN
foo(ONE) <= 1;
END behv;
This should do the trick for you. (Of course, if you plan to
synthesize, you've got about a 50/50 chance of this being
synthesizable.)
Charles F. Shelor cfsh...@acm.org
SHELOR ENGINEERING VHDL Training, Consulting, Models
3308 Hollow Creek Rd (817) 467-9367
Arlington, TX 76017-5346
Jeffrey S. Freedman
>Hi all,
>
>I'm a VHDL newbie and am having problems creating an array that is
>indexed via an enumerated type I've defined earlier. Here's a tiny
>sample that doesn't work:
>
>ENTITY test IS
>END test;
>
>ARCHITECTURE behv OF test IS
> TYPE enum is (ONE, TWO, THREE, FOUR, FIVE);
> VARIABLE foo : ARRAY (enum) OF INTEGER;
>BEGIN
> foo(ONE) := 1;
>END behv;
Sure, you can do what you want, and you've almost got it right. Here's a
version that works:
ENTITY test IS
END test;
ARCHITECTURE behv OF test IS
TYPE enum IS (one, two, three);
TYPE enum_array IS array(enum RANGE <>) of integer;
SIGNAL foo : enum_array;
BEGIN -- behv
foo(one) <= 1;
END behv;
-- Jeff
VhdlCohen
END test;
ARCHITECTURE behv OF test IS
TYPE enum is (ONE, TWO, THREE, FOUR, FIVE);
Type EnumArray_Typ is ARRAY (enum) OF INTEGER; -- define a type
BEGIN
Test_Lbl: process
VARIABLE foo : EnumArray_Typ; -- variables exist in processes ONLY
begin
foo(ONE) := 1;
wait;
end process Test_Lbl;
END behv;
======================================================
=========================
Ben Cohen is the author of an upcoming book "VHDL Coding Styles and
Methodologies
... an In-Depth Tutorial" to be published in July 95 by Kluwer
Academic Publishers.
Daniel S. Barclay
> ...
> -- Your code is not correct. Here is code that works.
> VARIABLE foo : EnumArray_Typ; -- variables exist in processes ONLY
And in subprograms.
> begin
> foo(ONE) := 1;
> wait;
> end process Test_Lbl;
> ...END behv;
Daniel
--
Daniel S. Barclay Compass Design Automation, Inc.
dan...@compass-da.com Suite 101, 5457 Twin Knolls Rd. Columbia, MD 21045 USA
"They listen hard, and act like they care.
How can they be so completely unaware
Of the truth? The answer is always denied me
So I introduce 'em to the killer inside me." - MC 900 Ft. Jesus
Kelly Hall
Robert> Hope this sets you on the right track.
Thanks to everyone who responded, both via news and via email.
The big problem was the anonymous type. VHDL makes me be more verbose
than I'd really like. The variable -vs- signal problem was a brain
hiccup on my part.
Robert Thompson
writes:
|> Hi all,
|>
|> I'm a VHDL newbie and am having problems creating an array that is
|> indexed via an enumerated type I've defined earlier. Here's a tiny
|> sample that doesn't work:
|>
|> END test;
|>
|> ARCHITECTURE behv OF test IS
|> TYPE enum is (ONE, TWO, THREE, FOUR, FIVE);
|> BEGIN
|> foo(ONE) := 1;
|> END behv;
|>
Hi Kelly,
You've raised a couple of points with your VHDL example. First off, here's
an example that does more or less what you want (I checked it through
Synopsys VSS V3.2a, so I think its OK)
ENTITY test IS
END test;
ARCHITECTURE behv OF test IS
TYPE enum is (ONE, TWO, THREE, FOUR, FIVE);
TYPE foo_bar IS ARRAY (enum) OF INTEGER;
SIGNAL foo : foo_bar;
BEGIN
foo(ONE) <= 1;
END behv;
There are a couple of changes to explain. The first, and the one I think you
really wanted to know about is that you must declare the type. VHDL doesn't
allow the Pascal style use of an anonymous type. Hence the declaration of
foo_bar.
The other problem, (and this could be a problem caused by trying to post a
small test case!) is that you cant declare a variable within an architecture.
If you did, it could be made visible to several processes and they could all
assign to it, causing obvious problems. (If you need to know more, look up
about "shared variables" in a book covering the new language definitions,
they weren't in the '87 version.) The obvious solution is to use a signal
declaration instead. Of course you can also declare foo as a variable in
either a process, procedure or function.
Hope this sets you on the right track.
Rob
Rob Thompson ro...@bristol.st.com
SGS-THOMSON Microelectronics "nothing unreal exists"