Synthesising hardware written in C
Donald MacRae
C++ into HDL. I've always assumed that this was 'ivory towers' research
which was interesting but of little use. However, I've just read in the
Electronic Times (UK mag) that many companies at DAC were exhibiting tools
to enable you to describe hardware in C/C++ and they could synthesis it into
efficient hardware. So does this mean C++ synthesis is becoming a practical
alternative to writing in VHDL.
If so, how can we put a stop to it. After all we've spent much time getting
to grips with VHDL and we dont want mere software engineers coming along,
designing hardware and stealing our jobs. :)
Don
Geir Harris Hedemark
> to enable you to describe hardware in C/C++ and they could synthesis it into
> efficient hardware. So does this mean C++ synthesis is becoming a practical
> alternative to writing in VHDL.
Try using the tools, and you will quickly see what they can and cannot do.
The company I work for has used high-level synthesis tools for a long
time. So far, no C/C++ tools can provide what we need. But then again,
we are tough customers.
Geir
John Reynolds
>
> Try using the tools, and you will quickly see what they can and cannot do.
>
> The company I work for has used high-level synthesis tools for a long
> time. So far, no C/C++ tools can provide what we need. But then again,
> we are tough customers.
I agree. Evaluate some of the tools and you will quickly see how restricted
you are and the things you cannot model. Stick with behavioral VHDL and the
world will be a better place.
The observation that one engineer had around here when discussing the
C/C++ vs. VHDL argument was that the more you restrict the C++ language by
using class templates, etc., the more you shave off the language so that
you can synthesize it, the more funky crap you add into the language to
simulate concurrency already found in VHDL, your "language" approaches
VHDL! So, just stick with VHDL and be done with it.
Many people argue "But VHDL is so hard to debug in." ... sorta true, but
not insurmountable.
-Jr
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| John Reynolds CEG, CCE, Next Generation Flows, HLA |
| Intel Corporation MS: CH6-210 Phone: 480-554-9092 pgr: 868-6512 |
| jrey...@sedona.ch.intel.com http://www-aec.ch.intel.com/~jreynold/ |
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Geir Harris Hedemark
> > The company I work for has used high-level synthesis tools for a long
> > time. So far, no C/C++ tools can provide what we need. But then again,
> > we are tough customers.
> I agree. Evaluate some of the tools and you will quickly see how restricted
> you are and the things you cannot model. Stick with behavioral VHDL and the
> world will be a better place.
We actually use DFL for behavioural code and synthesize it into VHDL,
which is synthesized into gates.
Yes, it works.
Geir