Any decent VHDL synthesis tool (Design Compiler from Synopsys,
Leonardo Spectrum or Precision Synthesis from Mentor,
Synplify from Synplicity, etc etc) will do this. Don't expect
it to be free though.
Altera Quartus and Xilinx XST are synthesis tools from the
device vendors that can be obtained free, at least in some
configurations. I'm not sure whether they offer schematic
viewers in the free versions, but they can definitely
create netlist outputs.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan...@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Mentor Graphics HDL designer has a code-to-graphics option (good for looking
at the hierarchy), for gate level most synthesis tools
(Synplify/Precision/Spectrum) have a RTL/Gatelevel schematic viewer. I am
not sure about Orcad though,
Hans.
www.ht-lab.com
"khansa" <khan...@yahoo.co.in> wrote in message
news:1f2e1ef.05040...@posting.google.com...
Xilinx ISE Webpack, which can be downloaded from Xilinx website, offer
such an option. It's called Schematic Viewer. It's not as good as the
40K dollars Synopsis or Synplicity tool, but it's free.
Hendra
Robert Schopmeyer/Veritools, Inc.
Aldec's Active-HDL has a Code2Graphics converter that works quite well
with VHDL and Verilog. It generates either block diagrams for structure
and finite state machine bubble diagrams for certain code templates.
It can convert to a block diagram virtually anything since it allows for
behavioral (concurrent assignments and processes) blocks in the document...
EG