Very less resource fixed point 32x32 bit multiplier and 32/32 divider

[Pratap]

Hi all,
I need to build an ASIC synthesizable fixed point 32x32 multiplier and
fixed point 32/32 divider with very less hardware resource for my
design.Speed is not at all a matter for me.
I can space 100s of cycles for my computaions.
Can anybody help me with the code (preferably in VHDL) or suitable
references?
Thanks,
Pratap

[whygee]

The first multi-cycle multiply/divide circuit was designed
long ago, look at this report from 1946 :
http://www.cs.unc.edu/~adyilie/comp265/vonNeumann.html
You only need enough bits storage for the operands, 32+32 FF,
as they are progressively replaced by computation results
in 32+32 cycles. It's a tricky but clever technique.

However, today, people use these techniques :
http://www.andraka.com/multipli.htm

Oh, and Wikipedia has some hints too :
http://en.wikipedia.org/wiki/Multiplication_ALU

yg

[Kevin Neilson]

If speed isn't an issue, you could put in a small 8- or 16-bit
microprocessor and small instruction ROM and let the C compiler take
care of the floating point operations.
-Kevin

[Kevin Neilson]

Sorry; I just noticed you said "fixed point" and not "floating point".
If you've got lots of time, you can make a multiplier from a single
adder and a divider from a single subtractor. Or if you wanted to be
smaller, you could go down to a single two-bit full adder, or use
bit-serial techniques. I would think, though, that in an ASIC, you have
plenty of gates, and simple "*" will be nicely synthesized into a small
core from the ASIC library.
-Kevin