Thanks to everyone for your replies. I am frustrated with extremely
arcane rationals for some of the things you can't do in VHDL. I have
been using the language for some 18 years now, but I don't use it all
the time. I do a project for a few weeks or months and then do some
more VHDL a year later typically. So in some ways I am a beginner every
time. lol I rely on cheat sheets to help me through the morass. One I
found recently is from Hardi Electronics and was designed to make a
pamphlet. It is organized for quick reference and has a lot more info
than the typical single sheet info form. But it is from 2000 and only
covers VHDL '93. Not much chance of an update as they were acquired by
Synplicity in 2007. Oh well...
MPCN_WIDTH : POSITIVE := 4
signal Bias : signed (MPCN_WIDTH+1 downto 0);
Bias <= (Bias'high-1 => '1', others => '0');
This is a concurrent assignment.
All the fancy explanation aside, I don't get why the tool can't figure
this out. In all fairness, the AHDL tool does suggest an option -relax
that will work around this issue, but I prefer to write code that meets
the standard, even if the standard is a bit anal.
Alan suggested that the aggregate would be valid...
s <= (Bias'high-1 => '1');
But this is not a bloody useful aggregate is it? In fact, it is only an
aggregate by definition I suppose.
I just found one problem with the Hardi cheat sheet. It is locked
against copying! I was going to copy a line talking about 'others', but
I can't. What is with people??? Why are they so frikin' paranoid?