stimulating a counter in modelsim
ed
i use aldec-hdl at work and stimulating a counter signal is as easy as
selecting the "counter" type and choosing a starting and incrementing
value. however, i have modelsim-xe installed on my laptop. what is the
easiest way to stimulate a counter in modelsim?
thanks in advance!
Ray Andraka
those stimulators are great. For those who don't know, the Aldec
environment has a stimulator property on each wave in the waveform
viewer. You can set the stimulators for each signal to various counts,
clocks, constants, patterns, hot keys etc without ever having to touch a
tcl file.
For modelsim, you will need to either write a testbench in VHDL or write a
tcl script to force the signals. Not as easy as the Aldec gui.
ed wrote:
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email r...@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Jonathan Bromley
> From: Ray Andraka [mailto:r...@andraka.com]
> Subject: Re: stimulating a counter in modelsim
>
> That's one of the things I like about Aldec. For quick and
> dirty sims,
> those stimulators are great. For those who don't know, the Aldec
> environment has a stimulator property on each wave in the waveform
> viewer. You can set the stimulators for each signal to
> various counts,
> clocks, constants, patterns, hot keys etc without ever having
> to touch a tcl file.
>
> For modelsim, you will need to either write a testbench in
> VHDL or write a
> tcl script to force the signals. Not as easy as the Aldec gui.
Ray's voice quite justly carries a lot of authority here, but
lest his position on this become "received wisdom" I feel I
should state the dissenting view: I think these GUI-driven
stimulus generators are truly horrible. I could never get on
with them - neither the "draw your desired stimulus waveform"
flavour, nor Aldec's "pick a ready-made signal from our kit".
In VHDL (or, as Ray points out, Tcl) you can say what you
want, with great clarity, with parameterisation, and with
the generality and expressiveness of a programming
language. Even for "quick and dirty", that's my choice.
As soon as you get even slightly close to "slow and clean" (!)
you really NEED a programming language to generate your
stimulus.
This is no criticism of Aldec. The GUI stimulus generator
is a tool like any other, to be used or ignored as you choose,
and there's nothing in Aldec's tool to stop me using VHDL.
Just a preference, of course. Your mileage may vary.
--
Jonathan Bromley
HDL Consultant
DOULOS - Developing Design Know-how
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Ray Andraka
more or less archives and documents the testing I did on a component. Still,
there are occasionally times when I have a small thing that I just want to do a
quick check on, and in those cases it is easier to use the canned stimulators
than to go through the rigor of writing a testbench.
Jonathan Bromley wrote:
--
Jonathan Bromley
> From: ed [mailto:agu...@cox.net]
> Subject: stimulating a counter in modelsim
>
> what is the
> easiest way to stimulate a counter in modelsim?
In all the discussion about GUI stimulus generators, we
forgot to give you an answer...
I'm guessing you have some device with an N-bit input
port, and you want to supply an N-bit binary count to
that port. Let's say your device under test (DUT) is...
entity MyDevice is
port (
-- I very much hope your device is synchronous,
-- and has an asynchronous reset input:
clock, reset : in std_logic;
-- And it has a "counter" input port, which
-- we will say is 8 bits wide just as an example:
CountInput: in std_logic_vector (7 downto 0);
-- and it probably has lots more ports...
...
...
);
end entity MyDevice;
OK, so now we need a test bench:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- needed for "unsigned" data type
-- The entity declaration for a test bench is always empty.
entity TestFixture is end entity TestFixture;
architecture Counting of TestFixture is
-- First a component declaration to match the DUT.
component MyDevice
port (
-- this port list must be exactly the same as
-- the port list in your MyDevice entity.
...
);
end component;
-- Now some signals to connect to the pins of the DUT.
signal clock, reset: std_logic;
signal Count: unsigned (7 downto 0);
-- and lots more for the outputs...
...
-- Don't forget to provide a signal that allows you to
-- bring simulation to a graceful halt.
signal Finished: boolean; -- is initially FALSE.
begin
-- Reset can be generated like this:
reset <= '1', '0' after 100 ns;
-- and clock like this:
clockGenerator: process
begin
clock <= '0';
while not Finished loop
wait for 5 ns;
clock <= not clock;
end loop;
wait;
end process;
-- and your count sequence goes like this.
-- We increment the count on FALLING edges of the clock,
-- so that the input has plenty of setup time before the
-- active (rising) clock edge.
countGenerator: process
begin
Count <= (others => '0'); -- initialise count to 0
wait until reset = '0'; -- allow reset to finish
for i in 1 to 300 loop -- as many times as you wish!
wait until clock = '0'; -- wait for falling clock edge
Count <= Count + 1;
end loop;
-- And now the stimulus is all finished...
Finished <= TRUE;
wait;
end process;
-- Finally you need to wire up the DUT.
-- Note that you can convert the unsigned signal Count
-- into a std_logic_vector as part of the port map - but
-- this works only in VHDL-93, so don't forget to enable
-- '93 mode in your simulator/compiler.
DUT: MyDevice port map (
clock => clock,
reset => reset,
CountInput => std_logic_vector(Count),
... -- wire up all the other ports too.
);
end architecture Counting;
Hope this helps, and you can see how to modify it to
meet your needs.
Brian Griffin
Or our can stimulate this interface with a sequence of force commands:
# Generate the clock signal
force clock 0 0, 1 5 -r 10
# In english, force clock to 0 at time 0,
# then 1 at time 5,
# then repeat every 10(ns)
# Now generate the count
force CountInput(0) 0 0, 1 10 -r 20
force CountInput(1) 0 0, 1 20 -r 40
force CountInput(2) 0 0, 1 40 -r 80
force CountInput(3) 0 0, 1 80 -r 160
force CountInput(4) 0 0, 1 160 -r 320
force CountInput(5) 0 0, 1 320 -r 640
force CountInput(6) 0 0, 1 640 -r 1280
force CountInput(7) 0 0, 1 1280 -r 2560
Of course you can use Tcl to parameterize this and provide other
patterns. The force command can take any number of value/time pairs.
-Brian