USE both rising edge and falling edge

[Chih-Hsun Lin]

Dear All :

I wish to use both rising edge and falling edge to double my clock rate.
I try the following code :

if clk'event and clk='1' then
dout<=din;
elsif clk'event and clk='0' then
dout<=din;
end if;

But it doesn't work. The simulation result from QUARTUS shows that the
"dout" is only changed in rising edge.

Could anyone kindly tell me how to code it ?

Best regards,
Lin CH

[Laurent Gauch]

Don't use two rising_edge or falling_edge in the same process
...
In VHDL synthesis : Process + edge detection = Flip-Flop
Also, you cannot find a Flip-Flop with 2 CLK inputs or with 1 CLK with
rising-edge detection and falling-detectoion, or never in CPLDs or FPGAs
... .

Maybe this is not possible in your case, but I think this is better and
easier if you double directly the clock rate of your CLK signal, or if you
try to think about a other SM possibility ...

--> If this is only a vhdl description for simulation (and not for
synthesis), I don't know ...

Laurent

Chih-Hsun Lin a écrit :

[Tony Nelson]

How about just:

if clk'event then
dout <= din;
end if;

However, a design using both rising and falling Clk edges may not synthesize
properly.
Tony

"Chih-Hsun Lin" <li...@mail.cern.ch> wrote in message
news:Pine.HPP.3.95a.100041...@hpl3tw03.cern.ch...

[a...@z.com]

Laurent Gauch wrote:

> Don't use two rising_edge or falling_edge in the same process
> ...
> In VHDL synthesis : Process + edge detection = Flip-Flop
> Also, you cannot find a Flip-Flop with 2 CLK inputs or with 1 CLK with
> rising-edge detection and falling-detectoion, or never in CPLDs or FPGAs
> ... .

This is not exactly true. Vantis (now Lattice) MACH5 EPLDs can toggle on both
edges of the clock and even have two clock enables, one for each clock edge.
It is true however that current synthesis tools do not like that.

Catalin

[Jamie Sanderson]

Lin;

Are you trying to create "hardware", or just a simulation model? If the
latter, then you can simply create a second signal which is "clk" delayed by
1/4 of the period, i.e. "delayed_clk <= clk after 10ns;". Then exclusive-OR
the "clk" and delayed "clk" signals to produce a 2x clock signal.

Since you mentioned Quartus, then I'm assuming you want this to work in an
FPGA or CPLD. Here you have a problem. It's very difficult to create large,
determinate delays in such a device. If you could specify the clock rate and
the target device, then you'll get a better response.

Regards,
Jamie

[Laurent Gauch]

Thank you Catalin,
I learn a good thing today
Laurent

a...@z.com a écrit :

[igla...@my-deja.com]

Hi,

I'm not sure what you exactly try to do but all FF have only one
edge clock.

you can try to play arround by making the clk signal a more complex one
thus getting posedge and negedge but the FF itself will work eventually
only with one edge.

doubling the clock might be one of the solution and you first need to
see that this double clock freq can be done in the device you want.
nevertheless the delay issue should not be too difficult as you can do
it using a nice solution I saw which work as followed :

The input clock is fed to the input of a XOR GATE as well as to the D
of a DFF.
The output of the DFF is fed back to the second input of the XOR GATE.
The output of the XOR GATE feeds the clock of the DFF and the doubled
clock.

using this approach you know that the clock will be width enough to
clock other FF's in the design.

there are other approach like using delay or using xor gate and so on
but I belive the above is a better one.

have a nice day

Illan

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