U1: comp1
port map(component_pin=>signal_node);
where signal_node has been declared previously right
below the currrent architecture.
My problem is, let say, if I want to port map component_pin
to a constant, e.g. '1' instead of signal_node, how am I
suppose to code that? I have tried
port map(component_pin=>'1');
but it doesn't seem to work.
Thanks for any hints.
>
> port map(component_pin=>'1');
>
>but it doesn't seem to work.
>
>Thanks for any hints.
>
>
constant assignments at the port map are a feature of VHDL '93.
MJ
Define a constant of type std_logic equalling '1':
constant ConstantValue : std_logic := '1';
U1: comp1 port map(component_pin => ConstantValue);
Cheers,
Rich
>Define a constant of type std_logic equalling '1':
>
>constant ConstantValue : std_logic := '1';
>U1: comp1 port map(component_pin => ConstantValue);
Hmmm ... I've tried that before; doesn't work. Maybe it's an FPGA
Express/VHDL'87 thing.
I create a "constant signal" instead:
signal vcc : STD_LOGIC;
begin -- architecture
vcc <= '1';
u1 : meshugga (pin1 => vcc ... );
works for me. ymmv.
--
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao.edu
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