Assigning std_logic_vector to 2D array ???
Peter Sommerfeld
I have a compiling piece of code but, being new to VHDL (I have been
writing AHDL up to now), I would like to know if it is the "right" way
to do it. I have an entity which produces as a 2D array:
--------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE myTypes IS
TYPE STD_LOGIC_2D IS ARRAY (Natural range <>, Natural range <>)
OF std_logic;
END myTypes;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.myTypes.all;
ENTITY io IS
PORT (
taps : OUT STD_LOGIC_2D(3 DOWNTO 0, 7 DOWNTO 0)
);
END io;
--------------------------------------------------------------
Trying to assign a range of bits from std_logic_vector to taps{0),
taps(1) and taps(2) did not compile. I ended up doing it with
individual bit assignment:
--------------------------------------------------------------
ARCHITECTURE io_inst OF io IS
SIGNAL fifo_out : STD_LOGIC_VECTOR(23 DOWNTO 0);
BEGIN
lp1:
FOR ii IN 0 TO 7 GENERATE
taps(0,ii) <= fifo_out(ii);
taps(1,ii) <= fifo_out(ii+8);
taps(2,ii) <= fifo_out(ii+16);
END GENERATE lp1;
END;
--------------------------------------------------------------
Is there any way to assign fifo_out(7 DOWNTO 0) to taps(0, 7 DOWNTO 0)
without assigning bit-by-bit?
Peter
Chris Rosewarne
You could try creating a 1-dimensional array of std_logic_vector's
instead, giving you a 1d array of 1d arrays, if you get my drift. You
can then assign to an entire std_logic_vector within the 1d array as
required.
If you wanted to stay with the 2d array, you can nest two
for..generate statements to assign each bit in the array individually.
When assigning to a 2d array, for a given assignment you will have to
provide both dimensions of the array, that is why just assigning to
taps(n) does not work.
regards,
Chris
peterso...@hotmail.com (Peter Sommerfeld) wrote in message news:<5c4d983.03021...@posting.google.com>...
Jim Lewis
array with two unconstrained ranges.
Use an unconstrained array of std_logic_vector. The
hitch is that the std_logic_vector must be constrained.
So for the second dimension being 8 bits:
type std_logic_2dx8 is array (nartural range <>) of
std_logic_vector(7 downto 0) ;
Now the following should work. Note minor changes to
the port declaration of taps. In the first solution,
I replaced the generate statement with a simpler method.
In the alternate code, I used the generate and showed
how to index each bit.
> LIBRARY ieee;
> USE ieee.std_logic_1164.all;
> USE work.myTypes.all;
>
> ENTITY io IS
> PORT (
> taps : OUT STD_LOGIC_2DX8(3 DOWNTO 0)
> );
> END io;
> ARCHITECTURE io_inst OF io IS
> SIGNAL fifo_out : STD_LOGIC_VECTOR(23 DOWNTO 0);
>
> BEGIN
taps(0) <= fifo_out(7 downto 0);
taps(1) <= fifo_out(15 downto 8);
taps(2) <= fifo_out(23 downto 16);
> END;
Alternately, you can use the generate statement,
but the above code is much easier to write:
> lp1:
> FOR ii IN 0 TO 7 GENERATE
> taps(0)(ii) <= fifo_out(ii);
> taps(1)(ii) <= fifo_out(ii+8);
> taps(2)(ii) <= fifo_out(ii+16);
> END GENERATE lp1;
Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:J...@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Nicolas Matringe
>
> Currently the language does not allow a two dimensional
> array with two unconstrained ranges.
Yes it does! It just doesn't allow an array of unconstrained arrays (such as an
array of unconstrained std_logic_vector)
type std_logic_2d is array (natural range <>, natural range <>) of std_logic;
is perfectly legal VHDL.
Nicolas
Ralf Hildebrandt
> type std_logic_2d is array (natural range <>, natural range <>) of std_logic;
>
> is perfectly legal VHDL.
ACK. - But not all synthesis tools will synthesize this.
Ralf