Asynchronous VHDL modeling
hardwarejobseeker
I am working on a project that aims at low power design of a
microcontroller. What I have done so far is:
1) Implemented clock gating methodologies and calculated the power
consumption before and after clock gating. It does reduce significant
amount of power.
My next approach is to make the design 'asynchronous'. I went over a
few docs that talk about asynchronous approaches in design (mostly
from the Asynchronous Logic group at Manchester University). However,
I am still not clear about asynchronous modeling at the behavioral
level in VHDL. I was trying to make the following "latch/FF" block
asynchronous, but have had no luck. Could anyone suggest on how to
make this block asynchronous, in VHDL? Any help would be appreciated.
library ieee;
use ieee.std_logic_1164.all;
entity latsync is
port
( clk :INOUT std_logic;
datain : INOUT std_logic;
dataout : OUT std_logic
);
end latsync;
architecture behav of latsync is
signal temp : std_logic;
begin
process (clk)
begin
if (clk = '1' and clk'event) then
temp <= datain;
dataout <= temp;
end if;
end process;
process
begin
clk <= '0';
wait for 50 ns;
clk <= '1';
wait for 50 ns;
end process;
process
begin
datain <= '0';
wait for 150 ns;
datain <= '1';
wait for 150 ns;
end process;
end behav;
Thanks,
-HWJS.
Ralf Hildebrandt
> My next approach is to make the design 'asynchronous'.
Simply inserting latches instead of flipflops will not work in general...
> begin
> process (clk)
> begin
> if (clk = '1' and clk'event) then
> temp <= datain;
> dataout <= temp;
> end if;
> end process;
This is a shift register. I can see no way to implement this
latch-based, with low amount of hardware.
I hope this would work (not tested):
-- define a state variable, that helps to build up the shift register
process(reset,clk)
begin
if (reset='0') then
state<='0';
elsif rising_edge(clk) then
state<=not(state); -- this is a FF!
end if;
end process;
-- your original temp-variable - represented with 2 latches
-- (same hardware amount like flipflops, but maybe
-- less power consumption)
process(clk,state,datain)
begin
if (clk='1') then
if (state='0') then
temp0<=datain; -- latch
else temp1<=datain; -- latch
end if;
end if;
end process;
-- prove, if the test of clock is nessecary - if not:
-- a simplex mux, else a latch is inferred
process(clk,state,temp0,temp1)
begin
if (clk='1') then -- latch
if (state='0') then
dataout<=temp1;
else dataout<=temp0;
endif;
end if;
end process;
Another problem may result in the muxed latch dataout. You synthesis
tool my generate a code, where the mux changes, but the latch is still
open. -> Solution: mux-choice and latch-enable have to be seperated.
Ralf
Uncle Noah
> My next approach is to make the design 'asynchronous'. I went ...
>
> begin
> process (clk)
> begin
> if (clk = '1' and clk'event) then
> temp <= datain;
> dataout <= temp;
> end if;
> end process;
Here you're wrong, since your coding implies edge-sensitive operation on
the clock input signal. Also the signal assignment part for passing datain
to dataout is wrong. Only the last assignment actually takes place. This is
due to the concept of delta timing in VHDL and the signal type attributes.
However, you can easily get an example on the net. In your case it should be:
process (clk,datain) -- i think for the asynch put data input is sens list
variable temp: STD_LOGIC;
begin
if (clk = '1') then
temp := datain; -- or use this: dataout <= datain;
dataout <= temp;
end if;
end process;
Something like this is the way to go.
Uncle "The G.B. Man" Noah
Renaud Pacalet
> Hi,
> I am working on a project that aims at low power design of a
> microcontroller. What I have done so far is:
> 1) Implemented clock gating methodologies and calculated the power
> consumption before and after clock gating. It does reduce
significant
> amount of power.
>
> My next approach is to make the design 'asynchronous'. I went over
a
> few docs that talk about asynchronous approaches in design (mostly
> from the Asynchronous Logic group at Manchester University).
However,
> I am still not clear about asynchronous modeling at the behavioral
> level in VHDL. I was trying to make the following "latch/FF" block
> asynchronous, but have had no luck. Could anyone suggest on how to
> make this block asynchronous, in VHDL? Any help would be
appreciated.
>
I think your problem is not a VHDL problem, it's an asynchronous
logic problem. Why do you want to model latches or dffs? If your
design is asynchronous and if you choose a delay insensitive
architecture then what you need is called C-muller, Merge,
2x2-Join, Wire, I-Wire, etc. Maybe I didn't understand what you
mean by asynchronous?
Regards,
--
Renaud Pacalet, ENST / COMELEC, 46 rue Barrault 75634 Paris Cedex 13
Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 | Mel : pac...@enst.fr
###### Fight Spam! Join EuroCAUCE: http://www.euro.cauce.org/ ######
hardwarejobseeker
could someone tell me, how will the following VHDL code look like if
it is made asynchronous.
I am not clear about the handshake protocol used for asynchronous
design.
entity latsync is
port
( clk :IN std_logic;
datain : IN std_logic;
dataout : OUT std_logic
);
end latsync;
architecture behav of latsync is
begin
process (clk)
begin
if (clk = '1' and clk'event) then
dataout <=datain;
end if;
end process;
end behav;
Thanks,
HWJS.
nk...@skiathos.physics.auth.gr (Uncle Noah) wrote in message news:<b7a879e0.0212...@posting.google.com>...
Mike Treseler
> Thanks for the responses,
> could someone tell me, how will the following VHDL code look like if
> it is made asynchronous.
> I am not clear about the handshake protocol used for asynchronous
> design.
>
> entity latsync is
> port
> ( clk :IN std_logic;
> datain : IN std_logic;
> dataout : OUT std_logic
> );
> end latsync;
It wouldn't have a clk input to start with.
Instead maybe Ready and Valid outputs.
If you intend to change your jobseeker status,
consider starting out with the easy stuff --
synchronous design.
-- Mike Treseler
Harish Y S
what you would expect on synthesizing it. What I mean is, the
synthesizers what we all use (like dc) are meant for synchronous
designs. Before thinking about ways to synthesize it (which is possible)
you should first understand the protocols involved.
I have explained the protocol aspects to understandable level on my
website @ http://hdlplanet.tripod.com Just go to the asynchronous
design section and you can find everything from fundamentals to
protocols. May be that helps you...
Regards,
Harish
http://groups.yahoo.com/group/hdlplanet
"hardwarejobseeker" <hardware...@yahoo.com> wrote in message
news:b45fd04d.02120...@posting.google.com
> Thanks for the responses,
> could someone tell me, how will the following VHDL code look like if
> it is made asynchronous.
> I am not clear about the handshake protocol used for asynchronous
> design.
--
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