Operator Overloading in VHDL

[vk...@my-deja.com]

Hi everyone,

I have a state machine in my design. And I am trying to use the state
bits as part of a combinatorial function as follows:

type statetype is (s0, s1, s2, s3, s4, s5, s6, s7, s8)
signal state: statetype;

signal we : std_logic;

I am trying to do this..

we <= dev_oe or s0 or s1 or s2 or s3 or s4 or s5 or s6 or s7 or s8;

And the tool complains.."No matching overload for or". I can see why it
is complaining.. but is there a standard library that I need to use that
has this taken care of? Or do I need a overloading function to be able
to get this to work.

I would appreciate any help from you

Thanks
Venu

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Before you buy.

[john...@my-deja.com]

In article <8priha$sku$1...@nnrp1.deja.com>,

You defined an enum type for states and the tool can not find the
corresponding OR operator on them.

I think what you can do is to create some true state bits, like
sb1, sb2 ..., all in the type of std_logic. Inside each states,
these signals get properly assigned. i.e in state s1: sb1 <= '1', etc.
then use sb's instead in your "we" assignment.

Alternatively, you can try outside of a process the following:

we <= '1' when (dev_en = '1' or state = s0 or state = s1 ...) else '0';

Hope this helps,

John

[Ray Andraka]

OR is not overloaded for you homespun enum.

instead, either inside the process:

if dev_oe='1' or state=S0 or state=s1... then
we<='1';
else we<='0';

or

case state is
when s0 | s1 | s2 | s3 |s4 |s5 | s6 | s7 |s8 =>
we<=dev_oe;
when others=>
we<='0';
end case;

or outside of the process

we<='1' when state=s0 or state=s1...

vk...@my-deja.com wrote:
>
> Hi everyone,
>
> I have a state machine in my design. And I am trying to use the state
> bits as part of a combinatorial function as follows:
>
> type statetype is (s0, s1, s2, s3, s4, s5, s6, s7, s8)
> signal state: statetype;
>
> signal we : std_logic;
>
> I am trying to do this..
>
> we <= dev_oe or s0 or s1 or s2 or s3 or s4 or s5 or s6 or s7 or s8;
>
> And the tool complains.."No matching overload for or". I can see why it
> is complaining.. but is there a standard library that I need to use that
> has this taken care of? Or do I need a overloading function to be able
> to get this to work.
>
> I would appreciate any help from you
>
> Thanks
> Venu
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email r...@andraka.com
http://www.andraka.com or http://www.fpga-guru.com