How to model a One-Shot?

Russ

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May 26, 1998, 3:00:00 AM5/26/98

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Hello,

Somewhat new to VHDL, but doing ok with the purely digital stuff.

Now I come across a one-shot (mono-stable-multivibrator) in a circuit I'm
converting to VHDL. Can anyone point me in a direction for handling such
an element?

Obviously, the component itself won't be part of the digital chip... but
I'd still like to run simulation on the entire system with the (simulated)
one-shot present. Can anyone show me how it's done? Thanks..

Russ

Paul J. Menchini

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May 26, 1998, 3:00:00 AM5/26/98

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Russ (nospam!rr...@geocities.com) wrote:
: Now I come across a one-shot (mono-stable-multivibrator) in a circuit I'm

: converting to VHDL. Can anyone point me in a direction for handling such
: an element?

: Obviously, the component itself won't be part of the digital chip... but
: I'd still like to run simulation on the entire system with the (simulated)
: one-shot present. Can anyone show me how it's done? Thanks..

entity OneShot is
port( Clk: in Bit;
Q, Qbar: out Bit);
end OneShot;

architecture Behavior of OneShot is
begin
process
constant HiTime: Time := <whatever>;
begin
Q <= '0';
Qbar <= '1';
wait until Clk = '1' and Clk'Event;
Q <= '1';
Qbar <= '0';
wait for HiTime;
end process;
end Behavior;

Note: the clock period had better be greater than HiTime. If it
isn't, this model will retrigger on the next rising edge of clock
following HiTime after the triggering edge....

Hope this helps,

Paul

Youn Ok Park

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May 27, 1998, 3:00:00 AM5/27/98

to

Russ (nospam!rr...@geocities.com) wrote:
: Hello,

: Somewhat new to VHDL, but doing ok with the purely digital stuff.

: Now I come across a one-shot (mono-stable-multivibrator) in a circuit I'm

: converting to VHDL. Can anyone point me in a direction for handling such
: an element?

: Obviously, the component itself won't be part of the digital chip... but
: I'd still like to run simulation on the entire system with the (simulated)
: one-shot present. Can anyone show me how it's done? Thanks..

: Russ
Here is one sample which is synthesizable.
Hope to be help!

-------------------------------------------------------
-- One-shot generator
--
-- +------------+
-- | |
-- --+ +-------------- : input
-- +------+
-- | |
-- -----+ +----------------- : output
--
-- --+ +---+ +---+ +---+ +---+
-- | | | | | | | | |
-- +--+ +--+ +--+ +--+ +- : clock
--
--
-- Written by Youn-Ok park, Jan. 1997
-- Copyright ETRI
--
library ieee;
use ieee.std_logic_1164.all;

entity ONE_SHOT is
port (
ignition: in std_logic;
clk : in std_logic;
rst : in std_logic;
o_one_shot: out std_logic
);

end ONE_SHOT;

architecture BEHAVIOR of ONE_SHOT is
signal async_latch : std_logic;
signal sync_latch : std_logic;
begin
process(ignition, rst, sync_latch) begin
if rst = '0' or sync_latch = '1' then
async_latch <= '0';
elsif ignition'event and ignition = '1' then
async_latch <= '1';
end if;
end process;

process(ignition, clk, rst, async_latch) begin
if rst = '0' then
sync_latch <= '0';
elsif clk'event and clk = '1' then
if sync_latch = '1' then
sync_latch <= '0';
else
sync_latch <= async_latch;
end if;
end if;
end process;

o_one_shot <= sync_latch;

end BEHAVIOR;

Following programe is Simulation file

-------------------------------------------------------
-- One-Shot generator
-- Simulation
-- Written by Youn-Ok Park,
-- Jan. 1997
-- Clocked one-shot, asyc latch + sync latch
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.ONE_SHOT;

entity TESTBNCH is
end TESTBNCH;

architecture stimulus of TESTBNCH is
component ONE_SHOT is
port (
ignition: in std_logic;
clk : in std_logic;
rst : in std_logic;
o_one_shot: out std_logic
);

end component;

constant PERIOD : time := 100 ns;
signal rst : std_logic;
signal clk : std_logic;
signal ignition : std_logic;
signal o_one_shot : std_logic;
signal done : boolean := false;

begin
DUT: ONE_SHOT port map (
ignition => ignition ,
clk => clk,
rst=>rst,
o_one_shot=>o_one_shot
);

CLOCK1: process
variable clktmp: std_ulogic := '0';
begin
wait for PERIOD/2;
clktmp := not clktmp;
clk <= clktmp; -- Attach your clock here
if done = true then
wait;
end if;
end process CLOCK1;

STIMULUS1: process
begin
ignition <= '0';
rst <= '0';
wait for PERIOD;
rst <= '1';
wait for 75 ns;
ignition <= '1';
wait for PERIOD * 4;
ignition <= '0';
wait for PERIOD * 4;

wait;
end process STIMULUS1;

end stimulus;

--
par...@mail.etri.re.kr
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+ Youn Ok Park, HL3HNK
+ Mobile Multimedia Section, ETRI,
+ P.O Box 106, Yusong,
+ Taejon, 305-350, Korea
+ http://sabina.etri.re.kr/~parkyo
+ (Phone) 82-42-860-6924
+ (FAX ) 82-42-860-6403
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Youn Ok Park

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Jun 9, 1998, 3:00:00 AM6/9/98

to

"Russ" <nospam!rr...@geocities.com> wrote:

>Hello,
>
>Somewhat new to VHDL, but doing ok with the purely digital stuff.
>
>Now I come across a one-shot (mono-stable-multivibrator) in a circuit I'm
>converting to VHDL. Can anyone point me in a direction for handling such
>an element?
>
>Obviously, the component itself won't be part of the digital chip... but
>I'd still like to run simulation on the entire system with the (simulated)
>one-shot present. Can anyone show me how it's done? Thanks..
>
> Russ

Here is one sample which is synthesizable.

Hope to eb help!

-------------------------------------------------------
-- One-shot generator
--
-- +------------+
-- | |
-- --+ +-------------- : input
-- +------+
-- | |

-- ---_--+ +----------------- : output

--
-- --+ +---+ +---+ +---+ +---+
-- | | | | | | | | |
-- +--+ +--+ +--+ +--+ +- : clock
--
--
-- Written by Youn-Ok park, Jan. 1997
--

end ONE_SHOT;

o_one_shot <= sync_latch;

end BEHAVIOR;

Simulation Vector file

-------------------------------------------------------
-- One-Shot generator
-- Simulation

-- Programmed by Youn-Ok Park