Hexadecimal Bit Vector Literals & std_logic

Johannes Steigerwald

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Jun 3, 2003, 4:41:22 AM6/3/03

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Hi all,

i try to use hexadecimal literals of the form X"BC95B5B5" for assigning
values to std_logic_vectors. The VHDL specification defines such
literals for bit vectors.
Now I face different behaviour with different compilers. Look at the
following code examples:

use ieee.std_logic_1164.all,
...
signal Bypass_Data : std_logic_vector(31 downto 0);
...
-- Version 1
Bypass_Data <= std_logic_vector'(X"BC95B5B5");
-- Version 2
Bypass_Data <= to_stdLogicVector(X"BC95B5B5"); -- to_stdLogicVector
defined in IEEE Package std_logic_1164
-- Version 3
Bypass_Data <= to_stdLogicVector(bit_vector'(X"BC95B5B5"));

* Synopsys vhdlan (Version 02.12) accepts Version 1 and Version 3, while
Version 2 gives me an error:
-- Bypass_Data <= to_stdLogicVector(X"BC95B5B5");
^
Error: analysis Parsing vhdl-409
[../../vhdl/ficontb/recvrblocktb.vhd:266]
Expression is ambiguous

* Cadence's NCVHDL accepts Version 2 and 3 while Version 1 yields an
error:
std_logic_vector'(X"BC95B5B5");
|
ncvhdl_p: *E,EXPTYP (test.vhd,12|45): expecting an expression of type
STD_LOGIC_VECTOR [7.3.4]

* Summit Designs Visual Elite Compiler (Version 3.5.2) accepts Version 2
and Version 3, while Version 1 yields an error:
ERROR: The expression must be of the type of the qualifier in ...

All three compilers accept the most clumsy Version 3. Is this the only
correct solution? Or who is right, Synopsys or the other two compilers?
Is there maybe another solution I have not yet tried (I also tried based
integer literals (16#BC95B5B5#) and conv_integer, however got errors
because the integer was too large meaning it cannot be represented by 32
Bits including sign bit)? Is there a difference between VHDL87 and
VHDL93 in this respect?

How I would love to just write 32h'BC95B5B5!

Thanks,
Johannes

Egbert Molenkamp

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Jun 3, 2003, 5:12:54 AM6/3/03

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"Johannes Steigerwald" <johannes.s...@ops.de> schreef in bericht
news:3EDC5F32...@ops.de...
..

> Bits including sign bit)? Is there a difference between VHDL87 and
> VHDL93 in this respect?

Yes.

See
http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html#bit_string_args

On May 7th a similar question was asked with subject "My tools diagree with
each other".
Here you will also an explanation.

Egbert Molenkamp

Johannes Steigerwald

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Jun 4, 2003, 6:46:58 AM6/4/03

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Thanks! Guess I will have to stick with the universal/clumsy way:
to_StdLogicVector(bit_vector'(X"..."))

--

rickman

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Jun 6, 2003, 1:58:47 PM6/6/03

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Johannes Steigerwald wrote:
>
> Thanks! Guess I will have to stick with the universal/clumsy way:
> to_StdLogicVector(bit_vector'(X"..."))
>
> Egbert Molenkamp wrote:
> >
> > "Johannes Steigerwald" <johannes.s...@ops.de> schreef in bericht
> > news:3EDC5F32...@ops.de...
> > ..
> > > Bits including sign bit)? Is there a difference between VHDL87 and
> > > VHDL93 in this respect?
> >
> > Yes.
> >
> > See
> > http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html#bit_string_args
> >
> > On May 7th a similar question was asked with subject "My tools diagree with
> > each other".
> > Here you will also an explanation.

Maybe I am missing something here. Since in VHDL93 the string can be
any of three types, including StdLogicVector, why can't you just type
cast the string as StdLogicVector? Do you still need to be compatible
with VHDL87?

--

Rick "rickman" Collins

rick.c...@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
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Hexadecimal Bit Vector Literals & std_logic_vector

Johannes Steigerwald

Egbert Molenkamp

Johannes Steigerwald

rickman