Error using to_unsigned
Vandana Goel
I get the following error when I complie the code below in
Modelsim.
Can you please point me to the mistake?
No feasible entries for subprogram to_unsigned
# ERROR: C:/vhdl/gen.vhd(111): Too many indexes for this array type.
# ERROR: C:/vhdl/gen.vhd(111): Bad object in expression:
std_logic_vector.
I want to increment rd_addr by 4 in line 111 and decrement by 3 later.
thanks,
-------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.aes_comp.all;
library work;
use work.aes_pkg.all; use work.aes_pkg;
entity key_gen is
port(clk : in std_logic;
rst : in std_logic;
key_in : in std_logic_vector(31 downto 0);
start_keygen: in std_logic;
rnd_key : out std_logic_vector(31 downto 0)
);
end key_gen;
architecture rtl of key_gen is
type state_type is (IDLE, K, B, no_op, R, X);
signal state, next_state: state_type;
signal j : std_logic_vector(3 downto 0);
signal sel1 : std_logic;
signal sel2 : std_logic;
signal sel3 : std_logic;
signal we_keyram : std_logic;
signal e_keyram_addr_cnt : std_logic;
signal first_time : std_logic;
signal key_cnt : std_logic_vector(1 downto 0);
signal X_cnt : std_logic_vector(1 downto 0);
signal keyram_in : std_logic_vector(31 downto 0);
signal rd_addr : std_logic_vector(5 downto 0);
signal wr_addr : std_logic_vector(5 downto 0);
signal word_32 : std_logic_vector(31 downto 0);
signal word_out : std_logic_vector(31 downto 0);
signal temp : std_logic_vector(31 downto 0);
signal byte0 : std_logic_vector(7 downto 0);
signal byte1 : std_logic_vector(7 downto 0);
signal byte2 : std_logic_vector(7 downto 0);
signal byte3 : std_logic_vector(7 downto 0);
begin --architecture
K_Ram : raminfr44x32 port map(clk => clk,
we => we_keyram,
a => wr_addr,
dpra => rd_addr,
di => keyram_in,
spo => open,
dpo => word_32);
--
fsm_proc: process (state, start_keygen, key_cnt, first_time, X_cnt)
begin
next_state <= IDLE;
X_cnt <= (others => '0');
first_time <= '0';
e_keyram_addr_cnt <= '0';
rd_addr <= (others => '0');
sel1 <= '0';
sel2 <= '0';
sel3 <= '0';
we_keyram <= '0';
case state is
when IDLE =>
X_cnt <= "00";
if (start_keygen = '1') then
next_state <= K;
else
next_state <= IDLE;
end if;
when K =>
-- key_cnt <= key_cnt + '1';
sel3 <= '1';
e_keyram_addr_cnt <= '1';
we_keyram <= '1';
first_time <= '1';
if (key_cnt = "11") then
next_state <= B;
else
next_state <= K;
end if;
when B =>
sel3 <= '0';
e_keyram_addr_cnt <= '0';
we_keyram <= '0';
first_time <= '0';
sel1 <= '1';
if (first_time = '1') then
rd_addr <= "000011";
else
rd_addr <=
std_logic_vector(to_unsigned(to_integer(unsigned(rd_addr))+ 4), 6);
--rd_addr + 4
end if;
next_State <= no_op;
when no_op =>
next_state <= R;
when R =>
sel1 <= '0';
sel2 <= '1';
e_keyram_addr_cnt <= '1';
we_keyram <= '1';
rd_addr <=
std_logic_vector(to_integer(unsigned(rd_addr)) - 3); -- rd_addr - 3
next_state <= X;
when X =>
sel2 <= '0';
rd_addr <= rd_addr + '1';
X_cnt <= X_cnt + '1';
if (X_cnt = "11") then
next_state <= B;
else
next_state <= X;
end if;
when others => null;
end case;
end process fsm_proc;
clk_proc: process (rst, clk)
begin
if (rst = '1') then
state <= IDLE;
elsif (clk'event and clk = '1') then
state <= next_state ;
end if;
end process clk_proc;
sweir
ieee.numeric_std libraries. The latter is the official library for
arithmetic. Unfortunately, your code is cut-off, so I can't see the section
that is failing.
Either use unsigned, or apply an unsigned cast where you want to do the
arithmetic:
signal some_vector : unsigned( 31 downto 0 ) ; //assumes you want to do
32 bit math
...
if( some_condition ) then
some_vector <= some_vector + 4 ;
...
if( some_other_condition ) then
some_vector <= some_vector - 3 ;
Regards,
"Vandana Goel" <vg...@aeptec.com> wrote in message
news:cd0b9174.02050...@posting.google.com...
Reto Zimmermann
> use ieee.std_logic_unsigned.all;
> use ieee.numeric_std.all;
As the previous poster mentioned, only use numeric_std.
> rd_addr <=
> std_logic_vector(to_unsigned(to_integer(unsigned(rd_addr))+ 4), 6);
Simplify this to
rd_addr <= std_logic_vector(unsigned(rd_addr) + 4);
since "+" is overloaded in numeric_std for mixed unsigned/natural
arguments.
Reto
Vandana Goel
> > use ieee.std_logic_unsigned.all;
> > use ieee.numeric_std.all;
on simulation/synthesis? The reason I am asking is because if I use
only numeric_std then I need to typecast all the statements like
rd_addr + '1'
in the code.
thanks for your help,
Vandana
Reto Zimmermann <re...@synopsys.com> wrote in message news:<3CD1BF03...@synopsys.com>...
VhdlCohen
I see no reason why it is a bad idea to use the Numeric_Unsigned package, which
covers overloaded operations on objects of type Std_Logic_Vector, and which
uses as its base the Numeric package.
From the package (sample here)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package NUMERIC_UNSIGNED is
function "+" (L, R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
...
If a user only wants to interpret std_Logic_vectors as unsigned, and maintain
ports as std_logic types, then the Numeric_Unsigned is a nice alternative
without the need for ugly type conversions.
Incidentally, this (very very strong typing) is one one of the main objections
of users of VHDL who are familiar (or have switched to) Verilog. Verilog is a
loosely typed language, but you don't see all these type castings. A
compromise for VHDL is to use the right package for the types you need.
Anyway, this is my opinion. I like to see code that is readable, without a lot
of type casting. Question: What is more important: the types of the objects or
the desired algorithms or functions?
--------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdl...@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------
Tim
> thanks, it worked!! What could be the implications if I use both
>
> > > use ieee.std_logic_unsigned.all;
> > > use ieee.numeric_std.all;
Unpredictability. And std_logic_unsigned is non-standard.
Mike Treseler
>
> > > use ieee.std_logic_unsigned.all;
> > > use ieee.numeric_std.all;
>
> on simulation/synthesis?
There is no real overlap on *these* two libraries for +, =, etc
since one covers std_logic_vector only and the other
covers unsigned vectors only.
The annoying conflict is between the built-in "=" for vectors and
the std_logic_unsigned "=" for std_logic vectors.
The numeric_std library does not have this problem.
> The reason I am asking is because if I use
> only numeric_std then I need to typecast all the statements like
> rd_addr + '1' in the code.
The numeric_std library can handle things like
if uns_vec + 1 = "00000011" . . . or
if uns_vec + "00000001" = 3
It can't handle std_vec + anything without a cast.
My solution for new code is to use unsigned as my default vector type.
If I inherit a large block of code that does what I need, I don't
bother changing types. However if large changes are made, I start
with a global search and replace of std_logic_vector with unsigned.
Lots of readers of this group don't like this method,
but it works for me.
-- Mike Treseler
VhdlCohen
>If I inherit a large block of code that does what I need, I don't
>bother changing types. However if large changes are made, I start
>with a global search and replace of std_logic_vector with unsigned.
>
>Lots of readers of this group don't like this method,
>but it works for me.
Perhaps the reason many readers do not like this, me included, is that the
interfaces to other components tend to be of std_logic_vector, unless
everything is changed to unsigned.
Thus, maintaining interfaces of type std_logic_vector is more conventional.
However, I'll agree with you if the subblocks that interconnect together are of
signed or unsigned, then those interfaces should be of those types for clarity.
ben cohen
the std_logic_unsigned "=" for std_logic vectors.
The numeric_std library does not have this problem.>
use the implicit declaration of "=".
----------------------------------------------------------------------------
Vandana Goel
numeric_std since there is no overlap but since std_logic_unsigned is
non standard it is preferable to use numeric_unsigned for statements
like rd_addr <= rd_addr + '1';
I am asking this because numeric_unsigned is not a default package in
modelsim.
vhdl...@aol.com (ben cohen) wrote in message news:<21cb1efc.02050...@posting.google.com>...
Mike Treseler
> Let me get this right. It's ok to use std_logic_unsigned with
> numeric_std since there is no overlap but since std_logic_unsigned is
> non standard it is preferable to use numeric_unsigned for statements
> like rd_addr <= rd_addr + '1';
It's probably best to choose one or the other.
Assuming you don't need signed types, your choices are:
1. Use a library that treats the type std_logic_vector
as unsigned. For example
synopsis:std_logic_unsigned
mentor : numeric unsigned
2. Use the ieee.numeric_std library and the unsigned
type for numeric functions.
Check the google archives for the arguments.
-- Mike Treseler