newby with a simple Type mismatch problem.
myself
2.1) I get this error
" Error L22/C0 : #0 Error:
C:/fndtn/active/projects/counter/counter.vhd line 22 Type mismatch
on left and/or right operand of binary operator. (VSS-523) "
the code is:
library IEEE;
use IEEE.std_logic_1164.all;
entity COUNTER is
port (
CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
COUNT: out STD_LOGIC_VECTOR (7 downto 0)
);
end COUNTER;
architecture COUNTER_arch of COUNTER is
SIGNAL Qtmp : std_logic_vector(7 downto 0);
begin
process (CLK, RESET)
begin
if RESET='1' then --asynchronous RESET active High
Qtmp <= "00000000";
elsif CLK'event and CLK='1' then --CLK rising edge
QTMP <= QTMP + 1 ; --THIS IS THE LINE THAT GIVES THE PROBLEM.
end if;
COUNT <= Qtmp;
end process;
I have tried a few diferent ways of doing this but get the same type
of mismach problems?
What is the correct way to do this without using a case statment?
Thanks
Martin
myself
"ieee.numeric_std.all;" and type unsigned
library IEEE;
use IEEE.std_logic_1164.all,ieee.numeric_std.all;
entity COUNTER is
port (
CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
COUNT: out unsigned (7 downto 0)
);
end COUNTER;
architecture COUNTER_arch of COUNTER is
SIGNAL Qtmp : unsigned(7 downto 0);
begin
process (CLK, RESET)
begin
if RESET='1' then --asynchronous RESET active High
Qtmp <= "00000000";
elsif CLK'event and CLK='1' then --CLK rising edge
QTMP <= QTMP + 1 ;
end if;
COUNT <= Qtmp;
end process;
Andy Peters
>Hi when i try to compile the following code (with xilinx foundation
>2.1) I get this error
>
>" Error L22/C0 : #0 Error:
>C:/fndtn/active/projects/counter/counter.vhd line 22 Type mismatch
>on left and/or right operand of binary operator. (VSS-523) "
There is no + operator that adds a std_logic_vector to an integer. You need
to add/change the indicated statements below.
>library IEEE;
>use IEEE.std_logic_1164.all;
use ieee.numeric_std.all; -- so we can use unsigned
>entity COUNTER is
> port (
> CLK: in STD_LOGIC;
> RESET: in STD_LOGIC;
> COUNT: out STD_LOGIC_VECTOR (7 downto 0)
> );
>end COUNTER;
>
>architecture COUNTER_arch of COUNTER is
SIGNAL Qtmp : unsigned(7 downto 0);
>begin
>
>process (CLK, RESET)
>
>begin
> if RESET='1' then --asynchronous RESET active High
> Qtmp <= "00000000";
> elsif CLK'event and CLK='1' then --CLK rising edge
> QTMP <= QTMP + 1 ; --THIS IS THE LINE THAT GIVES THE PROBLEM.
> end if;
>end process;
-- this needn't be in the process. If it IS in the process,
-- it needs a reset (COUNT <= (others => '0');
-- AND you need to be aware that there is a pipeline - COUNT will
-- take its value one tick AFTER Qtmp.
COUNT <= std_logic_vector(Qtmp);
you may also want to add some rollover protection so your simulation matches
your actual hardware.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Money is property; it is not speech."
-- Justice John Paul Stevens
Nicolas Matringe
>
> I am also new at this, and I am impressed by your answer. I had run
> this same example by Xilinx (I was trying to do a BCD down counter for
> some thumbwheel switches) and they did not have at answer. At a
> Xilinx/Insight seminar two days ago, the fellow there also went away
> from the STD_LOGIC_VECTOR for the port, as Andy did in his second
> message. And while I do understand the difference portwise (I think I
> do???), I still don't grasp the practical difference (the negative
> side) of changing the port to unsigned vs STD_LOGIC_VECTOR, although I
> am not at all comfortable making that change. Once again, thank you
> for sharing your knowledge so freely.
VHDL is strongly typed, ie you cannot "mix" different types in the same
operation. If you want to make an addition, both operands and the result
must be of the same type.
std_logic_vector is nothing but an array of bits, it does not represent
a number (well, it can but not necessarily). 1 is a number. You can not
add a number to an array of bit, it doesn't make any sense.
Using the 'signed' type, you define an array of bits that will be used
as a number so you can add 1 to it.
--
Nicolas MATRINGE DotCom S.A.
Conception electronique 16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11 92400 COURBEVOIE
Fax 00 33 1 46 67 51 01 FRANCE
Alan Fitch
writes
>thanks enyways i think i solved my problem with
>"ieee.numeric_std.all;" and type unsigned
>
>library IEEE;
>use IEEE.std_logic_1164.all,ieee.numeric_std.all;
>
> port (
> CLK: in STD_LOGIC;
> RESET: in STD_LOGIC;
> );
>end COUNTER;
>
>architecture COUNTER_arch of COUNTER is
>SIGNAL Qtmp : unsigned(7 downto 0);
>begin
>
>process (CLK, RESET)
>
>begin
> if RESET='1' then --asynchronous RESET active High
> Qtmp <= "00000000";
> elsif CLK'event and CLK='1' then --CLK rising edge
> QTMP <= QTMP + 1 ;
> COUNT <= Qtmp;
>end process;
>
process - in fact it is better to put it outside as a concurrent signal
assignment. The reasons are
a) it doesn't make much sense to put it in the process, because then the
assignment will be evaluated on changes of both clk and reset
b) some synthesis tools (namely Synopsys DC) will reject it as an error
regards
Alan
(strangely, a lot of tool are happy to have the assignment inside the
process, and then treat it as a concurrent assignment; e.g. Spectrum).
--
Alan Fitch
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, BH24 1AW, Hampshire, UK
Tel: +44 (0)1425 471 223 Email: alan....@doulos.com
Fax: +44 (0)1425 471 573
** Visit THE WINNING EDGE www.doulos.com **
mkoch
"Andy Peters" <apeters...@nospam.noao.edu.nospam> wrote:
> myself wrote in message <38f4c5b8...@news.magma.ca>...
> >Hi when i try to compile the following code (with xilinx foundation
> >2.1) I get this error
> >
> >" Error L22/C0 : #0 Error:
> >C:/fndtn/active/projects/counter/counter.vhd line 22 Type mismatch
> >on left and/or right operand of binary operator. (VSS-523) "
>
> There is no + operator that adds a std_logic_vector to an integer.
You need
> to add/change the indicated statements below.
>
> >library IEEE;
> >use IEEE.std_logic_1164.all;
>
> use ieee.numeric_std.all; -- so we can use unsigned
Or better (in my opinion) use one of packages from Synopsys:
STD_LOGIC_SIGNED or STD_LOGIC_UNSIGNED - then You don't need any other
changes...
>
> >entity COUNTER is
> > port (
> > CLK: in STD_LOGIC;
> > RESET: in STD_LOGIC;
> > COUNT: out STD_LOGIC_VECTOR (7 downto 0)
> > );
> >end COUNTER;
> >
> >architecture COUNTER_arch of COUNTER is
>
> SIGNAL Qtmp : unsigned(7 downto 0);
>
> >begin
> >
> >process (CLK, RESET)
> >
> >begin
> > if RESET='1' then --asynchronous RESET active High
> > Qtmp <= "00000000";
> > elsif CLK'event and CLK='1' then --CLK rising edge
> > QTMP <= QTMP + 1 ; --THIS IS THE LINE THAT GIVES THE PROBLEM.
> > end if;
> >end process;
> -- this needn't be in the process. If it IS in the process,
> -- it needs a reset (COUNT <= (others => '0');
> -- AND you need to be aware that there is a pipeline - COUNT will
> -- take its value one tick AFTER Qtmp.
> COUNT <= std_logic_vector(Qtmp);
>
> you may also want to add some rollover protection so your simulation
matches
> your actual hardware.
>
> -- a
> -----------------------------------------
> Andy Peters
> Sr Electrical Engineer
> National Optical Astronomy Observatories
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) noao \dot\ edu
>
> "Money is property; it is not speech."
> -- Justice John Paul Stevens
>
>
Sent via Deja.com http://www.deja.com/
Before you buy.
Andy Peters
>In article <8d2hag$13ul$1...@noao.edu>,
> "Andy Peters" <apeters...@nospam.noao.edu.nospam> wrote:
>> myself wrote in message <38f4c5b8...@news.magma.ca>...
>> >Hi when i try to compile the following code (with xilinx foundation
>> >2.1) I get this error
>> >
>> >" Error L22/C0 : #0 Error:
>> >C:/fndtn/active/projects/counter/counter.vhd line 22 Type mismatch
>> >on left and/or right operand of binary operator. (VSS-523) "
>>
>> There is no + operator that adds a std_logic_vector to an integer.
>You need
>> to add/change the indicated statements below.
>>
>> >library IEEE;
>> >use IEEE.std_logic_1164.all;
>>
>> use ieee.numeric_std.all; -- so we can use unsigned
>
>Or better (in my opinion) use one of packages from Synopsys:
>STD_LOGIC_SIGNED or STD_LOGIC_UNSIGNED - then You don't need any other
>changes...
I'll be the first to jump in and say: don't use
(non)std_logic_arith/unsigned/signed ... use numeric_std instead.
Thanks to Mench for that (non) thang ... I like it ...
Andy Peters
/*
>I am also new at this, and I am impressed by your answer. I had run this
same example by Xilinx (I was trying to do a BCD down counter for some
thumbwheel switches) and they did not have at answer. At a Xilinx/Insight
seminar two days ago, the fellow there also went away from the
STD_LOGIC_VECTOR for the port, as Andy did in his second message. And while
I do understand the difference portwise (I think I do???), I still don't
grasp the practical difference (the negative side) of changing the port to
unsigned vs STD_LOGIC_VECTOR, although I am not at all comfortable making
that change. Once again, thank you for sharing your knowledge so freely.
The thing to remember is that a std_logic_vector is simply a "string" of
bits. For instance, given:
"10100101" (hex A5)
Does that represent:
a) 165 decimal
b) -91 decimal
c) it depends
c) is correct, because VHDL has no way of knowing what those numbers
represent. This is where signed and unsigned come in. You declare a signal
(or variable) as signed or unsigned the same way you'd declare a
std_logic_vector:
signal num_u : signed (7 downto 0); -- a number from -128 to 127
signal num_s : unsigned (7 downto 0); -- a number from 0 to 255
signal blah : std_logic_vector(7 downto 0); -- a vector of std_logic
and you can do the usual math operations on those numbers. The conversion
from unsigned or signed to std_logic_vector is a simple cast:
blah <= std_logic_vector(num_u);
num_s <= signed(blah);
Note that declaring:
signal num_i : integer range 0 to 255;
is NOT the same as the declaration for the unsigned above. To convert,
you'll need to use one of the "to_" functions:
num_u <= to_unsigned(num_i, num_u'length);
which sorta looks like a typecast, but isn't. The 'length attribute tells
the function to_unsigned() how big a vector to make. You could also simply
use 8 because you know that num_u is eight bits wide, but that's not too
cool, eh?
The next trick is going from the integer to std_logic_vector. This involves
both the "to_" function and a typecast:
blah <= std_logic_vector(to_unsigned(num_i, blah'length));
This is one of the reasons why VHDL is called "verbose" or "wordy" or
whatever, but since the language is strongly typed, everything needs to be
spelled out. And while the statement above is kinda long, it's completely
clear about what's going on.
My personal preferences:
1) all ports are std_logic or std_logic_vector. things like ports driven by
more than one driver become obvious in simulation (gee, lookit all them
Xs!). You could use integer, or unsigned, or whatever. I don't. Your
choice. It is probably better to use std_ulogic(_vector); for some reason,
some synthesis tool app notes say that the tool prefers std_logic and others
prefer std_ulogic.
2) Counters get implemented as ranged integers. If they need to go out of
an entity, then they get converted to std_logic_vector, but the operations
done on them are as integers.
Your mileage may vary.
-- andy
Ray Andraka
the bits are controls to actuators, it could mean "Illegal state: You just
turned the one-of-a-kind-enormously-expensive-gizmo into a heap of scrap metal"
Andy Peters wrote:
> The thing to remember is that a std_logic_vector is simply a "string" of
> bits. For instance, given:
>
> "10100101" (hex A5)
>
> Does that represent:
>
> a) 165 decimal
> b) -91 decimal
> c) it depends
>
> c) is correct, because VHDL has no way of knowing what those numbers
> represent. This is where signed and unsigned come in. You declare a signal
> (or variable) as signed or unsigned the same way you'd declare a
> std_logic_vector:
>
>
--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email rand...@ids.net
http://users.ids.net/~randraka
Andy Peters
>Who said a STD_LOGIC VECTOR even has to represent a number? In the case
where
>the bits are controls to actuators, it could mean "Illegal state: You just
>turned the one-of-a-kind-enormously-expensive-gizmo into a heap of scrap
metal"
you're absolutely right!
further clarification for the newbies:
a std_(u)logic_vector is a bunch of bits concatenated for the convenience of
the user. any meaning assigned to any of the bits is purely in the mind of
the designer.
-- a
Edward Cheffetz
many months (years?) it would be before I can understand most of these questions
let alone the significance and innuendoes of the answers ... and I'm a baby
boomer to boot!!! Again, thank you - it helped me greatly!!!
Ed
Andy Peters wrote:
--
Edward Cheffetz
iPeripherals
860 236-2406
FAX 860 233-4949