newbie q: std_logic vs std

Matthew Todd Gavin

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Nov 30, 1994, 6:43:09 PM11/30/94

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Can someone please explain the differences between the std_logic
system, and the std_ulogic system? I have seen people using these logic
systems in their code postings. What logic values are in each? Are they
both "standards"? When VHDL-1076 first came out, what logic systems were
supported besides "bit = {0,1}"?

Thanks a lot,

Matt

--
*********************************************************
Matt Gavin BSEE U of Iowa '93
mtg...@uiuc.edu Go Iowa Hawks!!!!!
*********************************************************

Bert Molenkamp

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Dec 2, 1994, 3:28:23 AM12/2/94

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mg1...@eehpx27.cen.uiuc.edu (Matthew Todd Gavin) writes:
> Can someone please explain the differences between the std_logic
> system, and the std_ulogic system? I have seen people using these logic
> systems in their code postings. What logic values are in each? Are they
> both "standards"? When VHDL-1076 first came out, what logic systems were
> supported besides "bit = {0,1}"?
>

In the LRM 1076-1987 (and 1993) only type BIT is predefined.
Additional to the LRM there is the std_logic_1164 package.
The type std_logic is in fact not a TYPE but a SUBTYPE derived from
the type std_ulogic.
This subtype should in used if a signal is multiple driven (in that
case a resulotion function is necessary!). If a signal is NOT multiple
driven the std_ulogic type can be used. However, many users also uses
than the std_logic type.
The advantage of the unresolved type std_logic is:
checking of unintentionally multiple driven drivers.

Part of the std_logic_1164 package:

PACKAGE std_logic_1164 IS

-------------------------------------------------------------------
-- logic state system (unresolved)
-------------------------------------------------------------------
TYPE std_ulogic IS ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);
-------------------------------------------------------------------
-- unconstrained array of std_ulogic for use with the resolution function
-------------------------------------------------------------------
TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic;

-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic;

-------------------------------------------------------------------
-- *** industry standard logic type ***
-------------------------------------------------------------------
SUBTYPE std_logic IS resolved std_ulogic;

-------------------------------------------------------------------
-- unconstrained array of std_logic for use in declaring signal arrays
-------------------------------------------------------------------
TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic;

Bert Molenkamp
Dept. of Computer Science
University of Twente
PO Box 217
7500 AE Enschede
the Netherlands
email: mole...@cs.utwente.nl

Janick Bergeron

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Dec 3, 1994, 9:55:40 AM12/3/94

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In article <3bj2md$8...@vixen.cso.uiuc.edu>,

Matthew Todd Gavin <mg1...@eehpx27.cen.uiuc.edu> wrote:
>Can someone please explain the differences between the std_logic
>system, and the std_ulogic system? I have seen people using these logic
>systems in their code postings. What logic values are in each? Are they
>both "standards"? When VHDL-1076 first came out, what logic systems were
>supported besides "bit = {0,1}"?

Dilbert: "You guys have it easy with thoses sissies 1164 types. When
VHDL first came out, we only had 1's and 0's!"

The STD_ULOGIC, STD_LOGIC, STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR types
are the IEEE 1164 multi-valued logic types for VHDL modelling. They
can be found in the package IEEE.STD_LOGIC_1164. The logic values
are as follow:

'U' Unitialized (STD_ULOGIC'left)
'X'/'W' Strong/Weak unknown
'0'/'L' Strong/Weak 0
'1'/'H' Strong/Weak 1
'Z' High impedence
'-' Don't care (For synthesis only, treated as 'X')

The 'ULOGIC' types are unresolved versions of their "LOGIC" counterpart.
I personally prefer to use the former over the latter as a default blanket
type as it provide better documentation for the signals which DO require
to be resolved and error checking when I erroneously drive a signal more
than once.... The IEEE disagrees with me but then again, I'm not a member!

The IEEE is balloting a package to perform arithmetic operations on these
types called NUMERIC_STD. It is intended to replace vendor-supplied
arithmetic packages, such as Synopsys's STD_LOGIC_ARITH.

--
Janick Bergeron AnalySYS Inc. (613) 443-0428
Hardware Verification 25 Loiselle St, Suite 201 jan...@resudox.net
Consultant Embrun, ON, Canada, K0A 1W1
Synthesis - Verilog - VHDL

Protik Mia

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Dec 1, 1994, 12:01:20 PM12/1/94

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Matthew Todd Gavin (mg1...@eehpx27.cen.uiuc.edu) wrote:
: Can someone please explain the differences between the std_logic

: system, and the std_ulogic system? I have seen people using these logic

resolved vs. unresolved. If you have conflicting drivers of a net of
type std_logic, a resolution function is used to dictate the appropriate
value of the net vs. just assigning an unknown.

I think the values include 1,0,H,L,Z,X and U

- Protik

Paul J Menchini - Menchini and Associates

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Dec 9, 1994, 9:53:04 AM12/9/94

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Protik Mia (ps...@fc.hp.com) wrote:

: Matthew Todd Gavin (mg1...@eehpx27.cen.uiuc.edu) wrote:
: : Can someone please explain the differences between the std_logic
: : system, and the std_ulogic system? I have seen people using these logic

: resolved vs. unresolved. If you have conflicting drivers of a net of
: type std_logic, a resolution function is used to dictate the appropriate
: value of the net vs. just assigning an unknown.

: I think the values include 1,0,H,L,Z,X and U

The values are, in order U, X, 0, 1, Z, W, L, H, and -. U represents an
uninitialized net, and appears first so that this value becomes the default
value of all nets. - represents don't care; primarily useful for synthesis and
test vector description.

Ammar Muhiyaddin

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Dec 9, 1994, 1:35:33 AM12/9/94

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Hi,

I have just started using VHDL under Synopsis and I am facing a small
problem which looks trivial but could not solve it. I will appreciate
any help.

I was trying to write a behavioral model for an ADDER which adds two
integers. I checked my code with VHDLAN and had no problems. Then I was
trying to simulate it using VHDLDBX. The first simulation was OK. When I
tried to simulate it later, I got "Arithmetic operation overflow".

The problem is that the debugger is assuming a value for the input signal
which is out of range. I am not sure if this has to do with the code or
with the Synopsys package

The code is as follows:
-----------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity adder is
port(in1,in2 : IN INTEGER;
sum : OUT INTEGER);
end adder;

architecture impl of adder is
signal sum_signed: INTEGER;
begin
sum_signed <= in1 + in2;
sum <= sum_signed;
end impl;
-----------------------------

Many thanks in advance,

Ammar

MadEE

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Dec 12, 1994, 6:25:39 PM12/12/94

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In article <3c8trl$s...@nntp.ucs.ubc.ca>, amm...@ee.ubc.ca (Ammar
Muhiyaddin) writes:

From: Frank J. Ludicky, Sundstrand Aerospace

I don't know what your test-bench for this looks like but when signals
are initiallized before simulation, their initial values are set to either
a
user defined default which you would have to give in the entity
declaration or the left most value of the type, for integers, this would
probably be -2 ^ 31. If in1 and in2 are added together with each at the
left most value, the result will be a value outside the legal values for
the predefined integer type.

I hope this helps. FJL

newbie q: std_logic vs std_ulogic

Matthew Todd Gavin

Bert Molenkamp

Janick Bergeron

Protik Mia

Paul J Menchini - Menchini and Associates

Ammar Muhiyaddin

MadEE