Random number generator in VHDL

[pj...@my-deja.com]

Hi,

I've started with Verilog and so I'm quite new with VHDL. There is a random
number generator in Verilog but I didn't found one in VHDL. Is there an build
in command or an library with an random number generator aviable?

Regards

Jens Popp

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[Renaud Pacalet]

pj...@my-deja.com a écrit :

There is one that is really good from McDonnell Douglas
Aerospace-Defense & Electronics Systems:

http://rassp.scra.org/vhdl/models/math.html

And, as usual, you can find more in comp.lang.vhdl FAQ:

http://vhdl.org/comp.lang.vhdl/FAQ1.html#4.9

Regards,
--
Renaud Pacalet, ENST / COMELEC, 46 rue Barrault 75634 Paris Cedex 13
Tel. : 01 45 81 78 08 | Fax : 01 45 80 40 36 | Mel : pac...@enst.fr

[Extern]

Hi

No, there is no build in random generator available in VHDL.

A small and pretty good pseudo random generator I found in one of the
cources I followed was:

procedure Random (seed: inout natural; ran: out real) is

constant M : integer := 259200;
constant A : integer := 7141;
constant C : integer := 54773;
begin
Seed := (seed * A + C) mod M;
ran := REAL(seed) / REAL (m);
end;
-------------------
calling procedure:

...
process -- each process has its own seeds
variable seed : natural;
variable ran : real;
...
random (seed, ran); -- calling function
delay (I) := integer 9ran * 0.4) * 1 us;
....
----------------------
I hope this helps you

----------------------------------------------------------------
Johan Van Dyck
Johan.V...@philips.com
VLSI Design Engineer
Philips Leuven (Belgium)
Johan.V...@philips.com
----------------------------------------------------------------
<pj...@my-deja.com> wrote in message news:94rfoh$9k9$1...@nnrp1.deja.com...

[Ray Andraka]

There is one in the synposis library. I think the library name is
synopsis.distributions

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email r...@andraka.com
http://www.andraka.com or http://www.fpga-guru.com

[VhdlCohen]

That topic was discussed before, but for pseudo random bits in a vector, you
can use an LFSR. There is one at my site.
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[Brian Dickinson]

pj...@my-deja.com wrote:
>
>
> I've started with Verilog and so I'm quite new with VHDL. There is a random
> number generator in Verilog but I didn't found one in VHDL. Is there an build
> in command or an library with an random number generator aviable?
>

There's a simple uniform random number generator in the math_real
package.
Problem is that for copyright reasons, IEEE does not make this source
code available without payment. Your simulator may have the package
pre-compiled (look in the IEEE library for math_real) in which the
following instructions (from the draft version) seem to work:-

procedure UNIFORM (variable Seed1,Seed2:inout integer; variable
X:out real);
-- returns a pseudo-random number with uniform distribution in the
-- interval (0.0, 1.0).
-- Before the first call to UNIFORM, the seed values (Seed1, Seed2)
must
-- be initialized to values in the range [1, 2147483562] and
-- [1, 2147483398] respectively. The seed values are modified after
-- each call to UNIFORM.

Alternatively there's a more comprehensive package from Gnanasekaran
Swaminathan
available at the RASSP site:-

http://rassp.aticorp.org/vhdl/models/math.html

Here's the code I used to test the math_real UNIFORM procedure
*NB* this is VHDL'93 code!

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.all;

ENTITY math_rand IS
END math_rand;

ARCHITECTURE test OF math_rand IS
BEGIN

process
variable seed1 : integer := 23871;
variable seed2 : integer := 34452;
variable rndreal : real;
begin
for i in 0 to 20 loop
UNIFORM(seed1, seed2, rndreal);
report "rnd value: " & real'image(rndreal);
end loop;
end process;

END test;

B

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[VhdlCohen]

For pseudo-random simulation of bit vectors you can use an LFSR. There is one
at my site,