I have a project where I use top-level generics to size aspects of the design. I allow the synthesis tool to use the default bindings, but I like to assign different values during my behavioral testbench to speed things up.
Pre-synthesis simulation works great, but post-synthesis or post-route simulations crash because the testbench is trying to map generics to a synthesized component with no generics. This must come up often -- is there a standard strategy for this? Configuration
Code snippet from the testbench:
entity testbench is
generic (
HPIXELS : positive := 251;
VPIXELS : positive := 2
);
end entity;
architecture bhvr of testbench is
component camera_top
generic (
HPIXELS : positive := 320;
VPIXELS : positive := 240;
PIXDEPTH : integer range 1 to 16 := 16
);
port ( ... );
end component;
begin
uut : camera_top
generic map (
HPIXELS => HPIXELS,
VPIXELS => VPIXELS
)
port map ( ... );
end architecture;
Errors from simulator (ModelSim PE 10.0a):
# ** Warning: (vsim-8713) testbench.vhd(277): Bad default binding for component at 'uut'.
# (Generic 'PIXDEPTH' is not on the entity.)
# (Entity has no generics.)
# Region: /testbench/uut
# ** Warning: (vsim-8713) testbench.vhd(277): Bad default binding for component at 'uut'.
# (Generic 'VPIXELS' is not on the entity.)
# (Entity has no generics.)
# Region: /testbench/uut
# ** Warning: (vsim-8713) testbench.vhd(277): Bad default binding for component at 'uut'.
# (Generic 'HPIXELS' is not on the entity.)
# (Entity has no generics.)
# Region: /testbench/uut
Thanks all.
To do this you need to compile and produce a post route simulation
file for each and every set of generics that you would like to
simulate. In your case, for each specific combination of HPIXELS,
VPIXELS and PIXDEPTH that you want to simulate you need to do a new
build that has that specific setting and then repeat that process for
each set of settings. Then in the testbench you'll need to select
(via a generate statement) which specific post-route simulation you
want to instantiate.
Kevin Jennings
If it's just at the top level, another plan is to write a wrapper
architecture for your design with the original generics, and instance
your gate level design inside that wrapper. Of course there will be a
certain amount of manual faffing to keep the values of the generic in sync,
regards
Alan
--
Alan Fitch
That sounds do-able. Is there a slick way to pass the testbench an
argument so that it can generate the correct simulation without having
to manually update the file?
-Abel
Simulators will let you set top level generics. If you're using
Modelsim, then start it up and type 'vsim' <enter>. That will display
a dialog box that (among other things) lets you specify top level
generics. If you consider that slick, then use that method.
If not, then after you have the generics set up in the dialog box, hit
return and the resulting command line will be echoed into the
transcript window and the simulator will be started. Copy and paste
that command into whatever form you would consider to be slick.
KJ