vhdl port connection length error

[silve...@gmail.com]

Hi,

VHDL-illiterate here. I'm trying to hook up a xilinx logic probe in legacy VHDL code and am getting a complaint from the compiler that the expression length of the signal i'm feeding to the port doesn't match the expected size.

ila_inst: entity work.ila(rtl)

port map
(
clk => CLOCK,

probe0(31 downto 11) => std_logic_vector'(31 downto 11 => '0')

....

According to the compiler (modelsim), the zero-fill i'm sending to the probe0 port has a expression length of only 9 bits and thus doesn't match the port size. I believe the expression as written should be defining 21 bits of 0's?

Anybody have an idea what I am missing?

Cheers,
Stephen

[KJ]

On Monday, December 2, 2019 at 12:14:44 PM UTC-5, silve...@gmail.com wrote:
- Can you post the entity definition for 'ila' and the exact compiler error message?
- Assuming that 'probe0' consists of more bits than just '31 downto 11', where are the other bits being mapped? If probe0 does not have any more bits, then why are you port mapping to 'probe0(31 downto 11)' instead of just 'probe0'?

Kevin Jennings

[silve...@gmail.com]

Thanks for replying Kevin! probe0 does indeed have other bits being used, which I'm pasting below.

The entity definition is as follows:

COMPONENT ila PORT
(
clk : IN STD_LOGIC; -- input wire clk

probe0 : IN STD_LOGIC_VECTOR (31 downto 0); -- input wire [31:0] probe0
probe1 : IN STD_LOGIC_VECTOR (31 downto 0); -- input wire [31:0] probe1
probe2 : IN STD_LOGIC_VECTOR (31 downto 0); -- input wire [31:0] probe2
probe3 : IN STD_LOGIC_VECTOR (31 downto 0); -- input wire [31:0] probe3
probe4 : IN STD_LOGIC; -- input wire [0:0] probe4
probe5 : IN STD_LOGIC -- input wire [0:0] probe5
);
END COMPONENT;



probe0 in it's entirety is mapped as follows:

-- probe0(31 downto 11) => std_logic_vector'(31 downto 11 => '0'),
-- probe0(10 downto 10) => std_logic_vector'(10 downto 10 => SIG_A),
-- probe0( 9 downto 9) => std_logic_vector'(9 downto 9 => SIG_B),
-- probe0( 8 downto 0) => std_logic_vector(SIG_C),


Cheers,
Stephen

[KJ]

On Monday, December 2, 2019 at 1:13:05 PM UTC-5, silve...@gmail.com wrote:
You posted the component declaration but not the entity declaration for ila. They probably look nearly identical except for 'entity' vs 'component', but please post the entity as well since sometimes the two are different and a cause for compiler errors.

As a side note, since you are using direct entity instantiation (i.e. "ila_inst: entity work.ila(rtl)"), you don't need any component declaration. Components are only needed when you don't have the source code for a particular entity, usually because it is coming from some pre-compiled library from a vendor or something. This is off topic, but thought you might find it useful.

You say that probe0 is entirely mapped but what you showed for the mapping is in comments, not live code.

One line that looks suspicious is "probe0( 8 downto 0) => std_logic_vector(SIG_C)". Since SIG_A and SIG_B are one bit signals, does that mean SIG_C is as well? If it is, then you're trying to map a single bit signal to a nine bit vector in the port map which I think would produce the error message that you described. However, if it is still not compiling, you will need to post the following posted to diagnose:
- The entity definition for ila
- The full port map in the instantiation of ila
- Declarations of all signals that are included in the port mapping (i.e. SIG_A, SIG_B, SIG_C, etc.)

You didn't post the error message from Modelsim either. Since that error message will refer to a line number in your source file, you will also need to let us know exactly which line is being pointed to by Modelsim.

Kevin Jennings

[silve...@gmail.com]

I was hoping maybe it would be an obvious issue so I hadn't posted in full. Let me do all that now.

The block being instantiated is actually verilog, but here it is anyway:
module ila (
clk,


probe0,
probe1,
probe2,
probe3,
probe4,
probe5
);

input clk;


input [31 : 0] probe0;
input [31 : 0] probe1;
input [31 : 0] probe2;
input [31 : 0] probe3;
input [0 : 0] probe4;
input [0 : 0] probe5;


endmodule


And this is the full declaration of the instantiation, as well as the signal declarations being used:

PORT_0 :in unsigned(21 downto 0); (This is part of the port list of the calling block)

...

signal SIG_A : std_logic;
signal SIG_B : std_logic;
signal SIG_C : unsigned(8 downto 0);
signal SIG_D : unsigned(7 downto 0);
signal SIG_E : unsigned(21 downto 0);
signal SIG_F : std_logic;
signal SIG_G : std_logic;

...

ila_inst: entity work.ila(rtl)
port map
(
clk => CLOCK,

(line 330) probe0(31 downto 11) => std_logic_vector'(31 downto 11 => '0'),
(line 331) probe0(10 downto 10) => std_logic_vector'(10 downto 10 => SIG_A),
(line 332) probe0( 9 downto 9) => std_logic_vector'(9 downto 9 => SIG_B),
(line 333) probe0( 8 downto 0) => std_logic_vector(SIG_C),
(line 334) probe1(31 downto 8) => std_logic_vector'(31 downto 8 => '0'),
(line 335) probe1( 7 downto 0) => std_logic_vector(SIG_D),
(line 336) probe2(31 downto 22) => std_logic_vector'(31 downto 22 => '0'),
(line 337) probe2(21 downto 0) => std_logic_vector(SIG_E),
(line 338) probe3(31 downto 22) => std_logic_vector'(31 downto 22 => '0'),
(line 339) probe3(21 downto 0) => std_logic_vector(PORT_0),
(line 340) probe4 => SIG_F,
(line 341) probe5 => SIG_G
);




Below are the error messages.

Error (line 330): (vcom-1324) Range choice length is 21; length of expression of element association is 9.
Error (line 334): (vcom-1324) Range choice length is 24; length of expression of element association is 9.
Error (line 336): (vcom-1324) Range choice length is 10; length of expression of element association is 9.
Error (line 338): (vcom-1324) Range choice length is 10; length of expression of element association is 9.




The error messages seem to all be pointing at my attempts at zero-fill.

[KJ]

I don't see anything wrong with what you have posted, maybe it is some peculiarity about the Verilog to VHDL interface or maybe a tool bug. If you have paid support open a ticket. Didn't have time to put it in and play with it on my own.

For a workaround, you could define a zero vector constant like this
constant Zero: std_logic_vector(31 down to 0) := (others => '0');
Then on the port map take out an appropriate size slice to attach to the port.

Kevin Jennings

[silve...@gmail.com]

Thanks for the suggestion; I used that workaround and while it looks janky, at least it works. Could certainly be a tool issue; I'll consult our modelsim rep about it.

Cheers,
Stephen

[HT-Lab]

Before you consult your rep I suspect this is a bug in your version of
Modelsim as:

"probe(31 downto 11)=>std_logic_vector'(31 downto 11 =>'0'),"

works fine for me (Modelsim 2019.4). I do get a warning though:

vcom Message # 1514:
This is an informational warning. When an aggregate does not contain a
named element association that has a choice that is a range and that has
an expression that is of the type of the aggregate, when that aggregate
appears at a place where an OTHERS choice in the aggregate would not be
allowed, the direction of the aggregate is obtained from the direction
of the index subtype of the base array type (at the applicable index
position), not from the direction of the range choice(s) of the element
association(s).
The range choice(s) have no effect on the direction of the aggregate.
[DOC: IEEE Std 1076-2008 VHDL LRM - 9.3.3.3 Array aggregates]

Perhaps a simpler solution is:

"probe(31 downto 11)=>(others=>'0'),"

Hans
www.ht-lab.com

>
> Cheers,
> Stephen
>