Is there an equivalent to #define in VHDL

[Fred]

As you may gather I am fairly new to VHDL and would like my code to be
fairly readable.

In "C" there is the "#define" keyword which assigns constant expressions to
meaningful strings. Is there an equivalent in VHDL?

[valentin tihomirov]

assignment:
constant a: integer := 1;

conditional compilation:
--b: boolean, generic or constant
if (b) then
begin

-- or

if (b) generate
begin

[Fred]

"valentin tihomirov" <valentin_NO...@abelectron.com> wrote in
message news:c2svb4$1vmj24$1...@ID-212430.news.uni-berlin.de...

Many thanks for your input.

I have been using Xilinx ISE 6.1 Web-edition. This has a test bench
waveform generator which seems to give erroneous values to contants.

I have used:

entity sys_int is
generic (
CONSTANT nop_cs : std_logic := '0';
.
.
.

)

and later in a case statement:
cs <= nop_cs;

This compiles OK but when I use test bench waveform generator and then
produce a ".vhd" simulation file, I get "nop_cs" assigned a value of -9999.
If I use the integer type as per your suggestion I get type mismatch.

I was therefore wondering if I had missed something!

[valentin tihomirov]

> entity sys_int is
> generic (
> CONSTANT nop_cs : std_logic := '0';

I don't know about this usage of generics. The typical approach I use is:
entity E is
generic (
A: Integer;
b: Integer := DefB;

[Hans]

You can use a pre-processor like this one
http://www.klabs.org/richcontent/software_content/kpp.htm, otherwise a bit
of Tcl can do wonders :-)

Regards,
Hans.
www.ht-lab.com

"Fred" <fr...@abuse.com> wrote in message
news:4051e6be$0$31715$fa0f...@lovejoy.zen.co.uk...

[Chris Pruett]

No. VHDL has no preprocessor so there is no direct equivalent to
#define, #ifdef, and friends.

There are generics and generates which can do some of the function that
you might want to do with a preprocessor. Plus they have type-checking
and such. You may only use generate on concurrent blocks. You can
configure the width of a port with a generic but you can't flag the
ports in or out of a block.

I like generate and generics and use them often, but they are too
limited for some things. To deal with that, I wrap a third-party
preprocessor (filepp) around my VHDL code. Makefiles convert my
.vhd.pp files to .vhd before the compiler/simulator get to see them.

CP