Force/Release in VHDL
Tig...@my-dejanews.com
Hello,
Is there something similar to Verilog's Force/Release in VHDL? Thanks.
Tigers
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rka...@my-dejanews.com
Hi!
I am not a verilog guy, but surely in VHDL simulator you can force,
noforce(release) the desired signal.
Was this that you wanted, if not please explain what is it that you require
specifically.
Rajkumar....
In article <6ngmh7$j0p$1...@nnrp1.dejanews.com>,
Paul J. Menchini
bour...@my-dejanews.com wrote:
: In article <6ngmh7$j0p$1...@nnrp1.dejanews.com>,
: Tig...@my-dejanews.com wrote:
:> Is there something similar to Verilog's Force/Release in VHDL? Thanks.
: For those who don't know verilog, the procedural continous assignments
: (force/release and assign/deassign) are use essentially to separate the
: description of asynchronous set/reset from the synchronous behaviour.
: As far as I can tell, the force/release construct in Verilog was intended
: for debugging purpose in the context of Verilog-XL. If this is what you want
: -- i.e. interactively forcing a value on a signal and so ignoring the value
: computed by the model -- you should check the documentation of your simulator
: if it provides such kind of functionnality.
: In the context of a description, I'd use assign/deassign in Verilog instead
: of force/release. If you want to synthesize the description, I see no other
: way than rewriting your code. If you just want to simulate, you could have
: the same effect with an adequate resolution function, but I don't think that
: you'll have support from the standard packages, you'll write VHDL with a
: very verilogish style which will probably not be easily understood by VHDL
: people. Except if you have to port lot of verilog code making havy use of
: procedural continuous assignment with subtle effect (i.e. more than for
: asynchronous set or reset), I'd not take that path.
Guarded assignment to guarded signals will allow you to disconnect drivers
from signals without using a special value (e.g., 'Z'). This approach
is not often used, and many synthesis tools depreciate its use.
Paul
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bour...@my-dejanews.com
In article <6nrbmg$nrj$2...@mench.mench.com>,
"Paul J. Menchini" <me...@mench.mench.com> wrote:
>
> bour...@my-dejanews.com wrote:
: In article <6ngmh7$j0p$1...@nnrp1.dejanews.com>,
> : Tig...@my-dejanews.com wrote:
> :>Is there something similar to Verilog's Force/Release in VHDL? Thanks.
>
function]
>
> Guarded assignment to guarded signals will allow you to disconnect drivers
> from signals without using a special value (e.g., 'Z'). This approach
> is not often used, and many synthesis tools depreciate its use.
I had not though to guarded signals. I'm not familiar with them, but I do not
see how they could be used simply to emulate procedural continous assignments.
The continous assignement also disconnect the other drivers as well as
specifying a value (and the deassign/release restablish these drivers). As I
undertand them, the guard control only the driver of the guarded assignement.
Yours,
-- Jean-Marc
Paul J. Menchini
: In article <6nrbmg$nrj$2...@mench.mench.com>,
: "Paul J. Menchini" <me...@mench.mench.com> wrote:
:>
:> bour...@my-dejanews.com wrote:
: : In article <6ngmh7$j0p$1...@nnrp1.dejanews.com>,
:> : Tig...@my-dejanews.com wrote:
:> :>Is there something similar to Verilog's Force/Release in VHDL? Thanks.
:>
: [snipped solutions: rewriting the code or use non standard resolution
: function]
:>
:> Guarded assignment to guarded signals will allow you to disconnect drivers
:> from signals without using a special value (e.g., 'Z'). This approach
:> is not often used, and many synthesis tools depreciate its use.
: I had not though to guarded signals. I'm not familiar with them, but I do not
: see how they could be used simply to emulate procedural continous assignments.
: The continous assignement also disconnect the other drivers as well as
: specifying a value (and the deassign/release restablish these drivers). As I
: undertand them, the guard control only the driver of the guarded assignement.
What you say is true. Guards control only the driver of the guarded
assignment. There is no direct analogue. However, if one makes all the
guards mutually exclusive, then only one driver at a time will be
active, which presumably is the effect one is after.
bour...@my-dejanews.com
>
> Is there something similar to Verilog's Force/Release in VHDL? Thanks.
For those who don't know verilog, the procedural continous assignments
(force/release and assign/deassign) are use essentially to separate the
description of asynchronous set/reset from the synchronous behaviour.
As far as I can tell, the force/release construct in Verilog was intended
for debugging purpose in the context of Verilog-XL. If this is what you want
-- i.e. interactively forcing a value on a signal and so ignoring the value
computed by the model -- you should check the documentation of your simulator
if it provides such kind of functionnality.
In the context of a description, I'd use assign/deassign in Verilog instead
of force/release. If you want to synthesize the description, I see no other
way than rewriting your code. If you just want to simulate, you could have
the same effect with an adequate resolution function, but I don't think that
you'll have support from the standard packages, you'll write VHDL with a
very verilogish style which will probably not be easily understood by VHDL
people. Except if you have to port lot of verilog code making havy use of
procedural continuous assignment with subtle effect (i.e. more than for
asynchronous set or reset), I'd not take that path.
-- Jean-Marc