VHDL SRAM model for testbench?
db
I am looking to simulate my VHDL FPGA design and would like to design a
testbench that includes a VHDL model of an SRAM (32K x 8). Does anyone
have a good way of doing this? I was thinking of using textio
statements to use a file as the memory but am not quite sure how to go
about doing this, and even then am not sure this wouldn't slow the
simulator (ModelTech) to a crawl. Any suggestions would be
appreciated....thanks!!
db
remove <no spam> from reply
Robert Ho
db wrote:
> I am looking to simulate my VHDL FPGA design and would like to design
> a
> testbench that includes a VHDL model of an SRAM (32K x 8). Does
> anyone
> have a good way of doing this? I was thinking of using textio
> statements to use a file as the memory but am not quite sure how to go
>
> about doing this, and even then am not sure this wouldn't slow the
> simulator (ModelTech) to a crawl. Any suggestions would be
> appreciated....thanks!!
>
I would be interested also. I'm looking for VHDL RAM models..
Any pointers would be helpful.
Thanks,
Robert
Peter Ashenden
db wrote:
>
> I am looking to simulate my VHDL FPGA design and would like to design a
> testbench that includes a VHDL model of an SRAM (32K x 8). Does anyone
> have a good way of doing this? I was thinking of using textio
> statements to use a file as the memory but am not quite sure how to go
> about doing this, and even then am not sure this wouldn't slow the
> simulator (ModelTech) to a crawl. Any suggestions would be
> appreciated....thanks!!
A better way would be to use an array as the memory, and load it from a
file at initialization.
The DLX Case Study in The Designer's Guide to VHDL includes a memory in
the test bench. See Section 15.3, which includes a memory that is
"preloaded" with a program. See also Figure 18-9 in Section 18.2. It
describes a version of the memory that is intialized from a text file
using textio. Source code for the examples can be found by following
the links from my web page.
Hope this helps.
Cheers,
PA
--
Peter J. Ashenden Email: pet...@ececs.uc.edu
Visiting Scholar, Dept ECECS peter.a...@acm.org
University of Cincinnati Phone: +1 513 556 4756
PO Box 210030 Fax: +1 513 556 7326
Cincinnati OH 45221-0030, USA
http://www.cs.adelaide.edu.au/~petera/
(includes PGP public key)
Charles F. Shelor
Robert Ho wrote:
>
> db wrote:
>
> > I am looking to simulate my VHDL FPGA design and would like to design
> > a
> > testbench that includes a VHDL model of an SRAM (32K x 8). Does
> > anyone
> > have a good way of doing this? I was thinking of using textio
> > statements to use a file as the memory but am not quite sure how to go
> >
> > about doing this, and even then am not sure this wouldn't slow the
> > simulator (ModelTech) to a crawl. Any suggestions would be
> > appreciated....thanks!!
> >
>
> Any pointers would be helpful.
>
> Thanks,
>
> Robert
There was a VHDL Times article about modeling memory. You can find
it on-line at: http://vhdl.org/vhdl_intl/vltimes/53-SHELOR.html
Other sources for models are:
http://www.vhdl.org/vi/fmf/
http://www.erc.msstate.edu/mpl/vhdl/html/models
http://rassp.scra.org/vhdl/models.html
--
Charles F. Shelor cha...@efficient.com
Efficient Networks, Inc 'ATM for the Desktop'
4201 Spring Valley, Suite 1200 http://www.efficient.com/
Dallas, TX 75244 (972) 991-3884
Brian Drummond
Robert Ho <r...@sarnoff.com> wrote:
>
>I would be interested also. I'm looking for VHDL RAM models..
>Any pointers would be helpful.
>
In addition to the other suggestions posted, some RAM manufacturers
provide models of their own devices.
http://www.micron.com/ has some, including burst synchronous SRAM.
- Brian
Edwin Naroska
Hi,
Robert Ho wrote:
>
> db wrote:
>
> > I am looking to simulate my VHDL FPGA design and would like to design
> > a
> > testbench that includes a VHDL model of an SRAM (32K x 8). Does
> > anyone
> > have a good way of doing this? I was thinking of using textio
> > statements to use a file as the memory but am not quite sure how to go
> >
> > about doing this, and even then am not sure this wouldn't slow the
> > simulator (ModelTech) to a crawl. Any suggestions would be
> > appreciated....thanks!!
> >
>
> I would be interested also. I'm looking for VHDL RAM models..
> Any pointers would be helpful.
>
Take a look at "The Hamburg VHDL archive" located at
http://tech-www.informatik.uni-hamburg.de/vhdl/vhdl.html
Further, check out the FAQ at
http://vhdl.org/comp.lang.vhdl/
In Part 1 section 3.2 you will find a list of web sites containing
VHDL models.
Bye,...
Edwin
--
-----------------------------------------------------------
Edwin Naroska
Computer Engineering Institute
(Lehrstuhl fuer Datenverarbeitungssysteme)
University of Dortmund
44221 Dortmund
Germany
email: ed...@ds.e-technik.uni-dortmund.de
phone: ++49 231 7552406
fax: ++49 231 7553251
-----------------------------------------------------------
APP01
If you are targeting an Orca FPGA or have access to the Orca Foundry tools,
there is a tool called SCUBA which is synthesis compiler. This tool has the
ability to also create behavorial models for RAM's and some other elements. As
far as Ram elements, you enter teh number of data bits, address bits, wether
the ram is sync or async, single port or dual port and it with spit out a
behavorial VHDL, Verilog, and even Synthesizable VHDL, Verilog, and EDIF
netlists that target an orca device.
Regards,
Tony
Peter Ashenden
See also S. Mohanty, K. Maheswaran and S. Haruyama, "SCUBA: An HDL
Data-Path/Memory Module Generator for FPGSs,", Proc. VIUF Fall 1997
Conference, Arlington, VA (October 1997), pp. 135-142.