Access by hierarchical names - through VHDL bindings?
Brendan Lynskey
I'm using a testbench that accesses Verilog objects through hierarchical
names.
I'm adapting it to access its (Verilog) design through a VHDL binding.
Would this be expected to work?
Thanks in advance,
--
Brendan Lynskey
Comodo Research Lab
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Madhury
Objective: Seeking an opportunity of growth and responsibility in a
company working on cutting edge technologies.
Summary: I am a permanent resident of US with industry experience of
about 7 years in design verification of ASIC/FPGA's in processors,
communication, networking applications with various EDA tools.
Technical Skills:
Applications: Embedded Controller, Microprocessors,
Ethernet, ISA, Token Ring, PCI, SDH, SONET,
VIX, RTCP, RTP.
Languages:Verilog, C, E-Specman, Perl, Vera
EDA Tools:Verilog -XL, VCS, Synopsys synthesis tool,
Chrysalis ver 2.4, Specman, Matlab,
Virsim,SignalScan, Undertow, TBP,
Mentor Graphics DFT tool, Primetime-STA,
Modelsim
Operating Systems:UNIX, Windows NT/95/98
Professional Experience
07/00 - Present Zaiq Technologies
Verification Engineer
Client : Acme Packet
Project: Design Verification of statistics calculation FPGA.
This project involves the verification of a FPGA which does statistics
gathering of the network packets (VIX protocol) sitting on the communication
router board, which is used to route high-value traffic from the edge of one
carrier network to another carrier network edge
My contributions:
1. Develop testplan for the verification of FPGA.
2. Build the verification environment for the FPGA.
3. Integrated the VIX BFM models from AMCC, modified to suit them to test
the stats FPGA.
4. Written testcases to verify that the FPGA captures the VIX packets
correctly.
5. Verification of Jitter/Latency calculations of RTCP and RTP packets.
Client : Intel
Project: Design Verification of SONET/SDH framer and T3/E3/T1/E1 mapper.
The device is a high density 155Mbit/s SONET/SDH framer and T3/E3/T1/E1
mapper chip, used to transfer data between the line interface side, which
carries a small number of high bandwidth signals and the terminal interface
side, which
carries a large number of lower bandwidth signals.
My Contributions:
1. Verification of TU-12/TU-11 Overhead bytes.
Client : Acme Packet
Project: Design Verification of Communication Router.
This project involves the verification of a communication router that is
used to route high-value traffic from the edge of one carrier network to
another
carrier network edge.
My Contributions:
1. Developed a script to extract the models from the router netlist.
2. Implemented the necessary models to compile the router netlist
3. Verified MPC7450 PPC access to various components on the board.
Client : Astral Point Communications Inc.
Project: Design Verification of Optical Switch System
The optical switch system is designed to support SONET STS switched
networks. It supports interface rates from DS3 to OC-192.
My Contributions :
1. Verification of Slave Bus, to test the communication protocol between
MPC8260 PPC and the DCC core.
2. Verification of DCC FPGA, which extracts the overhead bytes in OC48,
OC12.
3. Verification of Backplane, to test the connectivity of all the boards.
4. Installation of PCI transactor into the verification environment.
Client : Teradyne Inc.
Project: Design Verification of a DSP Chip
This DSP chip is used for mixed signal testing, which requires analog
stimulus and produces analog output that must be captured and analyzed. The
functionality is implemented in two ASIC's and one FPGA.
My Contributions :
1. Implemented matlab models to extract coefficients for different filters.
2. Developed a C model for noise shaped sine wave data generator.
3. Did Unit level testing of three major blocks in the FPGA.
4. Developed test cases for system level verification of the Asic.
5. Verification of 8B/10B encoder and Decoder.
6. Verified data and address are DC balanced for the communication link
12/97 - 06/00 AMD Singapore pvt ltd.
Design Engineer
Project: Design Verification of Micro-Controller
This microcontroller is a highly integrated system-on-chip that provides a
high degree of functionality. It combines a 32bit Am5x86 CPU with a
complete set of integrated peripherals suitable for both real time and
PC/AT compatible embedded applications.
My Contributions :
1. Did block level verification of Address Decode Unit.
2. Did the code coverage using Vericov.
3. Wrote the testcases for PIC (Programmable Interrupt Controller).
4. Involved in formulating the testplans at the system level.
5. Developed SDRAM buswatcher.
6. Used formal verification to ensure rtl matches the fixes done to the
netlist.
7. Developed testcases in Specman to test the bugs discovered in the
silicon.
Project: Design Verification of Ethernet Controller
This Ethernet controller is a highly integrated 32 bit full duplex,
10/100Mbps, designed to address high-performance system application
requirements.
My Contributions :
1. Formulated the testplans for the system level testing of MMP module.
2. Developed the testcases to test the various features of MMP.
3. Involved in the system level testing of Transmit and Receive Operation.
4. Used Vericov tool to improve code coverage.
03/96 - 10/97 Wipro Infotech - Global R&D
Project Engineer
Project: Design Verification of SNET ETHERNET and TOKEN RING Controller
SNet ETHERNET and TOKEN RING controller serves the purpose of a gateway
from Server Net to single Token Ring and dual Ethernet LANs. The FPGA
designed was targeted at ACTEL library. Since FPGA is one time programmable
lot of emphasis is there on the TESTBENCH for this project.
My Contributions :
1. Developed and verified verilog models of all the models on the board like
Quicc, DRAM, 060 proc, TIOGA, C26 proc.
2. Developed the testbench, integrating all the models developed to test
FPGA.
3. Did gate level tests of the fpga.
4. Did performance analysis of the board to determine the time available for
the cpu to execute the functions.
Project: Architectural analysis of FRASIC (Frame-Relay ASIC)
The FRASIC is a communication controller. This provides 4 full duplex
ports that can be configured for T1/E1, HSSI, V.35, X.21 interfaces.
My Contributions :
1. Involved in the design, architecture and performance calculations of
FRASIC
2. Did modeling of UPC for CBR traffic.
3. Memory model was developed.
Education :
1996 Masters in Electrical Engg. MSEE
Indian Institute of Technology Kharagpur (8.67 CGPA)
1994 Bachelor of Engineering BSEE (Electrical Engineering)
Andhra University Visakhapatnam (85.5%)
Training Mentor Graphics-DFT tool
Synopsys - Primetime, STA tool
Honors
NMS (National Merit Scholarship) from VIII grade to B.E
Gold medalist of Andhra University (A.U) in E.E.E
M.Tech thesis awarded second by Indian Society for Technical education
(ISTE)
"Achiever's Award" for excellent performance in AMD Singapore.
Two excellence awards in Zaiq Technologies.
Andre Powell
No you cannot 'normally' access any signal or port that is below the top
level entity in VHDL. However there if you are
using Modelsim there is a capability to look at the lower levels by using
some special techniques. See the manual. Specman uses this technique in
their hook files.
Best Regards
Andre'
Yves Tchapda
> Hi.
>
> I'm using a testbench that accesses Verilog objects through hierarchical
> names.
>
> I'm adapting it to access its (Verilog) design through a VHDL binding.
>
> Would this be expected to work?
>
> Thanks in advance,
Hi Brendan,
This is simulator specific. Modelsim version 5.5 or newer allows you
to access a signal down the hierarchy, and map it to another signal.
For instance, if you want to view a signal /top/dut/inst/test_point do
the following
libbrary modelsim_lib;
use modelsim_lib.util.all;
entity top is
end entity top;
architecture rtl of top is
signal top_test_point;
begin
process
begin
init_signal_spy("/top/dut/inst/test_point, "/top_test_point",1);
...
end process
end rtl;
Other simulators may do it differently, as this is not inherent in the
language.
Cheers
Yves
Srinivasan Venkataramanan
"Yves Tchapda" <yves.t...@phyworks-ic.com> wrote in message
news:434d10fb.03021...@posting.google.com...
<SNIP>
> Hi Brendan,
> This is simulator specific. Modelsim version 5.5 or newer allows you
> to access a signal down the hierarchy, and map it to another signal.
Cadence's NCSIM has a similar feature named nc_mirror starting from
version 4.1. The accompanying document explains how to use it, but is very
similar to Modelsim's Signalspy. They have also added nc_deposit, nc_force
etc. I am not sure if similar features are supported in Modelsim too.
Regards,
Srinivasan
<SNIP>
--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt Ltd. - an Intel company
Bangalore, India
I don't speak for Intel