vhdl code for a 16x8 bit dual port ram

[ameya]

I need the code for the dual port ram. a single 8 bit will do . if i
have for a 16x8 then its very nice of u. the specs are :

If data is to be written from both sides thne priority has to be
assigned to one side. Simultaneous read & write from same location
results in corect data being writen into the memory but invalid data
presented at reading port. simultaneous reads from the same location
allowed.

[Christian Cier-Zniewski]

Hi,

download the Actel HDL coding style guide at www.actel.com .
On page 86 you will find the behavioral model (vhdl source code) for
a register-based 8x8 Dual-Port RAM.
You will also find 3 generics defined as width, depth and addr.
Simply modify width and depth to fit you needs.

Christian

[SVillios]

You might also try www.cypress.com,
look up their application notes.

>Subject: vhdl code for a 16x8 bit dual port ram
>From: ameya_...@yahoo.com (ameya)
>Date: 10/28/02 2:20 AM US Mountain Standard Time
>Message-id: <5503c066.0210...@posting.google.com>
>
>

[mahdiha...@gmail.com]

-------------------------------------------------------
2 -- Design Name : ram_dp_ar_aw
3 -- File Name : ram_dp_ar_aw.vhd
4 -- Function : Asynchronous read write RAM
5 -- Coder : Deepak Kumar Tala (Verilog)
6 -- Translator : Alexander H Pham (VHDL)
7 -------------------------------------------------------
8 library ieee;
9 use ieee.std_logic_1164.all;
10 use ieee.std_logic_unsigned.all;
11
12 entity ram_dp_ar_aw is
13 generic (
14 DATA_WIDTH :integer := 8;
15 ADDR_WIDTH :integer := 8
16 );
17 port (
18 address_0 :in std_logic_vector (ADDR_WIDTH-1 downto 0); -- address_0 Input
19 data_0 :inout std_logic_vector (DATA_WIDTH-1 downto 0); -- data_0 bi-directional
20 cs_0 :in std_logic; -- Chip Select
21 we_0 :in std_logic; -- Write Enable/Read Enable
22 oe_0 :in std_logic; -- Output Enable
23 address_1 :in std_logic_vector (ADDR_WIDTH-1 downto 0); -- address_1 Input
24 data_1 :inout std_logic_vector (DATA_WIDTH-1 downto 0); -- data_1 bi-directional
25 cs_1 :in std_logic; -- Chip Select
26 we_1 :in std_logic; -- Write Enable/Read Enable
27 oe_1 :in std_logic -- Output Enable
28 );
29 end entity;
30 architecture rtl of ram_dp_ar_aw is
31 ----------------Internal variables----------------
32
33 constant RAM_DEPTH :integer := 2**ADDR_WIDTH;
34
35 signal data_0_out :std_logic_vector (DATA_WIDTH-1 downto 0);
36 signal data_1_out :std_logic_vector (DATA_WIDTH-1 downto 0);
37
38 type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto 0);
39 signal mem : RAM (0 to RAM_DEPTH-1);
40 begin
41
42 ----------------Code Starts Here------------------
43 -- Memory Write Block
44 -- Write Operation : When we_0 = 1, cs_0 = 1
45 MEM_WRITE:
46 process (address_0, cs_0, we_0, data_0, address_1, cs_1, we_1, data_1) begin
47 if (cs_0 = '1' and we_0 = '1') then
48 mem(conv_integer(address_0)) <= data_0;
49 elsif (cs_1 = '1' and we_1 = '1') then
50 mem(conv_integer(address_1)) <= data_1;
51 end if;
52 end process;
53
54 -- Tri-State Buffer control
55 data_0 <= data_0_out when (cs_0 = '1' and oe_0 = '1' and we_0 = '0') else (others=>'Z');
56
57 -- Memory Read Block
58 MEM_READ_0:
59 process (address_0, cs_0, we_0, oe_0, mem) begin
60 if (cs_0 = '1' and we_0 = '0' and oe_0 = '1') then
61 data_0_out <= mem(conv_integer(address_0));
62 else
63 data_0_out <= (others=>'0');
64 end if;
65 end process;
66
67 -- Second Port of RAM
68 -- Tri-State Buffer control
69 data_1 <= data_1_out when (cs_1 = '1' and oe_1 = '1' and we_1 = '0') else (others=>'Z');
70
71 -- Memory Read Block 1
72 MEM_READ_1:
73 process (address_1, cs_1, we_1, oe_1, mem) begin
74 if (cs_1 = '1' and we_1 = '0' and oe_1 = '1') then
75 data_1_out <= mem(conv_integer(address_1));
76 else
77 data_1_out <= (others=>'0');
78 end if;
79 end process;
80
81 end architecture;

[Nicolas Matringe]

Le 03/09/2014 16:50, mahdiha...@gmail.com a écrit :
> On Monday, October 28, 2002 12:50:09 PM UTC+3:30, ameya wrote:
>> I need the code for the dual port ram. a single 8 bit will do . if i
>> have for a 16x8 then its very nice of u. the specs are :

[...]

> -------------------------------------------------------
> 2 -- Design Name : ram_dp_ar_aw
> 3 -- File Name : ram_dp_ar_aw.vhd
> 4 -- Function : Asynchronous read write RAM
> 5 -- Coder : Deepak Kumar Tala (Verilog)
> 6 -- Translator : Alexander H Pham (VHDL)

[...]

Well I sincerely hope the original poster didn't wait almost 12 years
for you to give an answer

Nicolas

[sarves...@gmail.com]

Sir actually I want vhdl code of dual port ram, and I didn't gets proper way information about DPR though internet

Sir its kind request to please
Send code on this email mithles...@gmail.com

[Charles Bailey]

Just about any textbook or reference book on VHDL will have examples of
a one-port ram, and probably a dual port ram also.

Charles Bailey

[kunalk...@gmail.com]

I am unable to find the code on the given link.