aldec elaboration problem

[hawaiian techer]

Hello,
I'm using the aldec 4.1 vhdl compiler. I have a test bench that I'm
writing that contains 3 top-level entities. The entities are targeted
for separate chips and the test bench is testing to make sure they all
play nicely together. The entities each have their own project file
and .lib file. I declare the entities in the test bench with:

library chip1;
library chip2;
library chip3;

entity BusTestEnt is
end BusTestEnt;

architecture uPBusTestArch of uPBusTestEnt is

-- Component declaration of the "top_chip1(chip1toparch)" unit
-- File name contains "top_chip1" entity: .\src\top.vhd
component top_chip1
port(
--pinout
);
end component;
for all: top_chip1 use entity chip1.top_chip1(chip1toparch);

begin
inst1: top_chip1 port map(
--map pins to local signals
);

and so on for the other two entities.

It compiles with no errors but when I run the simulation, I can't view
signals in chip2 or chip3. I've tried changing the order in which I
delcare/instantiate the chips but I always get only chip1 in the
simulation window. I check the elaboration.cfg and aldec is only
elaborating chip1. And chip1 behaves as though it wasn't connected to
the other two chips. Anybody seen this before? Any suggestions on how
I can simulate all 3 chips? I'm assuming I'm missing something small
like a compiler setting but I went through those and they seemed ok.

TIA,
Gabe

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[y_na...@my-deja.com]

Hi

Could you please explain how your arch and ent binded?
Also pls tell you really did not use use-clause or just omitted on
postin.

Regards.

In article <94ssnk$hti$1...@nnrp1.deja.com>,

[hawaiian techer]

In my original posting, I used:

entity lib entity architecture
\/ \/ \/ \/

for all: top_chip1 use entity chip1.top_chip1(chip1toparch);

after the component/end component; block and it compiles with out
warnings but the entity doesn't appear in simulation.

I've also tried a configuration block at the end of the file like:

configuration TESTBENCH_FOR_Test_Top of TestEnt is
for TestArch
for inst1: chip1
use entity chip1.top_chip1(chip1toparch);
end for;
end for;
end TESTBENCH_FOR_Test_Top;

and this compiles with the following error:

Error: COMP96_0213: <file>.vhd : (622, 7): Component instance "inst1 :
chip1" not found.

I'm don't know how else to instantiate it besides how i did in my
original posting below.

TIA,
Gabe

In article <94v1tr$2v7$1...@nnrp1.deja.com>,

[y_na...@my-deja.com]

Hi

Same to Aldec's, I also not found your inst1:chip1 ....

> I've also tried a configuration block at the end of the file like:
>
> configuration TESTBENCH_FOR_Test_Top of TestEnt is
> for TestArch

> for inst1: chip1 -- < **** ? **** >

> use entity chip1.top_chip1(chip1toparch);
> end for;
> end for;
> end TESTBENCH_FOR_Test_Top;
>

> Error: COMP96_0213: <file>.vhd : (622, 7): Component instance "inst1 :
> chip1" not found.

Am I right to understand your source as follows?

configuration TESTBENCH_FOR_Test_Top of TestEnt is
for TestArch

for inst1: TOP_CHIP1 --< **** **** >

use entity chip1.top_chip1(chip1toparch);
end for;
end for;
end TESTBENCH_FOR_Test_Top;

> > > library chip1;
> > > library chip2;
> > > library chip3;
> > >
> > > entity BusTestEnt is
> > > end BusTestEnt;
> > >

> > > architecture uPBusTestArch of BusTestEnt is
> > > component TOP_CHIP1
> > > ...
> > > end component;
> > > for all: TOP_CHIP1 use entity chip1.top_chip1(chip1toparch);
> > >
> > > begin
> > > inst1: TOP_CHIP1 port map( --< **** **** >

> > > --map pins to local signals
> > > );
> > >

You look skillfull enough to solve this issure.
So I suppose you found out all of these already.
Only thing I'd like to say is Just be carefull of naming identifiers.
( Just from my impression. When you write a wrapper, it becomes much
reallistic )

Best regards.

[y_na...@my-deja.com]

Hi
Due to some language difficulty, I am not sure if following is
something what you intended for original post, but I hope it
could be something of your help as this compiles into my MTI
and functions ok.

--
-- compile this into your library *lib1*
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_ARITH.all;
library lib1;

entity EntX is port ( PIN: in integer; PCLK: in bit; POUT: out
integer); end EntX;

architecture A1 of EntX is
begin
process (PCLK)
begin
if PCLK'event and PCLK='1' then
POUT <= PIN+1;
end if;
end process;
end A1;

architecture A2 of EntX is
begin
process (PCLK)
begin
if PCLK'event and PCLK='1' then
POUT <= PIN+2;
end if;
end process;

end A2;

--
-- compile this into your library *lib2*
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_ARITH.all;
library lib2;

entity EntX is port ( PIN: in integer; PCLK: in bit; POUT: out
integer); end EntX;

architecture B1 of EntX is
begin
process (PCLK)
begin
if PCLK'event and PCLK='1' then
POUT <= PIN-1;
end if;
end process;
end B1;

architecture B2 of EntX is
begin
process (PCLK)
begin
if PCLK'event and PCLK='1' then
POUT <= PIN-2;
end if;
end process;
end B2;

-- compile this last into your *work*.

--
-- TestBench
--

library lib1;
library lib2;

entity TB is end;
architecture TBA of TB is
signal SigI1,SigI2 : integer := 0;
signal SigO1,SigO2 : integer;
Signal SigCLK: bit;

component EntUT
port( PIN : in integer;
PCLK: in bit;
POUT: out integer);
end component;

for inst1: EntUT use entity lib1.EntX(A1);
for inst2: EntUT use entity lib2.EntX(B2);

begin

SigCLK <= not(SigCLK) after 10 ns;
inst1: EntUT
port map(PIN => SigI1, PCLK=>SigCLK, POUT => SigO1);
inst2: EntUT
port map(PIN => SigI2, PCLK=>SigCLK, POUT => SigO2);

process(SigCLK)
begin
if SigCLK'event and SigCLK='1' then
SigI1 <= SigO1;
SigI2 <= SigO2;
end if;
end process;
end TBA;

Sorry for my poor english and to be long > all.

Best regards.

[Srinivasan Venkataramanan]

Hi,
I think you have confused us with 2 contradictory postings. Here you
say:

hawaiian techer wrote:
>
> In my original posting, I used:
>
> entity lib entity architecture
> \/ \/ \/ \/
> for all: top_chip1 use entity chip1.top_chip1(chip1toparch);
>
> after the component/end component; block and it compiles with out
> warnings but the entity doesn't appear in simulation.
>

Does it mean that you don't see signals of your "chip1"?

In your first posting, I see:

> It compiles with no errors but when I run the simulation, I can't
> view signals in chip2 or chip3.

I take it from here on that "chip1" instance works fine but not
chip2 & chip3.

> I've also tried a configuration block at the end of the file like:
>
> configuration TESTBENCH_FOR_Test_Top of TestEnt is
> for TestArch
> for inst1: chip1
> use entity chip1.top_chip1(chip1toparch);
> end for;
> end for;
> end TESTBENCH_FOR_Test_Top;
>
> and this compiles with the following error:
>
> Error: COMP96_0213: <file>.vhd : (622, 7): Component instance "inst1 :
> chip1" not found.
>

Again if I see refer to your full code (from previous post)

> for all: top_chip1 use entity chip1.top_chip1(chip1toparch);
>
> begin
> inst1: top_chip1 port map(
> --map pins to local signals
> );
>

So your "chip1" was named as "top_chip1" and hence the CFG should
have been

configuration TESTBENCH_FOR_Test_Top of TestEnt is
for TestArch

-- for inst1: chip1
-- ^^^^^^^
for inst1: top_chip1

use entity chip1.top_chip1(chip1toparch);
end for;
end for;
end TESTBENCH_FOR_Test_Top;

Also I don't see bindings for chip2 & chip3 - did you leave them out
fro brevity or indeed did you miss them in your code? If second is the
case, a proper CFG would be

configuration TESTBENCH_FOR_Test_Top of TestEnt is
for TestArch

for inst1: top_chip1

use entity chip1.top_chip1(chip1toparch);
end for;

for inst1: top_chip2
use entity chip2.top_chip2(chip2toparch);
end for;

for inst1: top_chip3
use entity chip3.top_chip3(chip3toparch);
end for;

end for;
end TESTBENCH_FOR_Test_Top;

(Again there is a conflict in the testbench entity name & arch name
among your posts)

> I'm don't know how else to instantiate it besides how i did in my
> original posting below.
>

I guess the instantiation is fine but not the binding.

HTH,
Srini

--
Srinivasan Venkataramanan (Srini)
ASIC Design Engineer,
Chennai (Madras), India

[y_na...@my-deja.com]

I hope you've got noticed my kidding points. (^^)
1. integers are not ranged
2. clocks are boubled on T.B
3. reg's are not cleared
What I really meant is to concentrate into your issure
of configuration only. I personally prefer to separate
config's into other files so that I get much free on writing
my T.Bs.

[hawaiian techer]

Srinivasan Venkataramanan <sr...@realchip.com> wrote:
> Hi,
> I think you have confused us with 2 contradictory postings. Here you
> say:

You are correct, I misspoke in one of my postings. Obviously in my
actual code I didn't name everything 'chipN' but I thought that'd be
easier to read in the abstract example I was giving. So I lost track
of how I was renaming everything.

> >
> > entity lib entity architecture
> > \/ \/ \/ \/
> > for all: top_chip1 use entity chip1.top_chip1(chip1toparch);

The above is correct.

> >
> > after the component/end component; block and it compiles with out
> > warnings but the entity doesn't appear in simulation.
> >
>
> Does it mean that you don't see signals of your "chip1"?

I see the signals of chip1 but not 2 or 3. I can't see the signals
internal to chip2 or 3 and if I assign values to the input signals
(signals local to the testbench, stimulus signals) the signals mapped
to the outputs remain at 'U' even if the output eqn is out <= in or
whatever.

>
> In your first posting, I see:
>
> > It compiles with no errors but when I run the simulation, I can't
> > view signals in chip2 or chip3.
>
> I take it from here on that "chip1" instance works fine but not
> chip2 & chip3.
>

You are correct. Chip1 functions normally but chips2 and 3 don't.

> > I've also tried a configuration block at the end of the file like:

I posted the configuration block wrong in the last post.

> > configuration TESTBENCH_FOR_Test_Top of TestEnt is
> > for TestArch
> > for inst1: chip1

^-top_chip1

> > use entity chip1.top_chip1(chip1toparch);
> > end for;
> > end for;
> > end TESTBENCH_FOR_Test_Top;
> >
> > and this compiles with the following error:
> >
> > Error: COMP96_0213: <file>.vhd : (622, 7): Component
instance "inst1 : chip1" not found.

^-top_chip1

> >
>
> Again if I see refer to your full code (from previous post)

As I said, you were correct. So I what I had along is what you're
suggesting and it still fails to compile. I hope I'm explaining this
well enough.

> Also I don't see bindings for chip2 & chip3 - did you leave them out
> fro brevity or indeed did you miss them in your code?

Brevity

> > I'm don't know how else to instantiate it besides how i did in my
> > original posting below.
> >
>
> I guess the instantiation is fine but not the binding.

My latest attempt to fix this problem has been to not use libraries. I
copied all the source files into a new testbench project. I got rid of
all the library chip1; etc statements at the beginning and I had to
rename some entities that were in more than one chip to avoid conflicts
but after all that I still have the same problem of it not compiling
with the config block or if it does compile (by using use statements
after component declaration) it doesn't simulate chip2 and chip3. I
don't understand why it picks chip1 to simulate. If I declare things
in a different order, it still picks chip1. I have the testbench
entity/arch pair set as the top-level entity. Is that correct? If I
set chip2 or chip3 as the top-level entity it simulates that chip but
not the other two.

[hawaiian techer]

I'm totally embarrassed about this, but I figured out my mistake.
Within my instantiations that didn't show up, I had a signal called TPN
which was a std_logic_vector. I was ignoring them for the testbench
and so I had
TPN => (others <= '0'),
...
but it should be
TPN => (others => '0'),

I guess the compiler was thinking I was doing some sort of assignment
statement and not instantiation.

I feel so lame. Such a silly typo... I thought I should post this to
remind other newbies about this possible mistake and hopefully save
someone the trouble I went through.

Thanks all for your input,
gabe

[Srinivasan Venkataramanan]

Hi,

hawaiian techer wrote:
>
> I'm totally embarrassed about this, but I figured out my mistake.
> Within my instantiations that didn't show up, I had a signal called TPN
> which was a std_logic_vector. I was ignoring them for the testbench
> and so I had
> TPN => (others <= '0'),
> ...

Are you sure you did this in a port map? AFAIK this should not
compile, it is ILLEGAL (SImli does report an error for this).

> but it should be
> TPN => (others => '0'),
>
> I guess the compiler was thinking I was doing some sort of assignment
> statement and not instantiation.
>

I would rather suspect that the compiler is buggy here.

[me...@mench.com]

On Wed, 31 Jan 2001 22:12:05 GMT, hawaiian techer
<au_ga...@my-deja.com> wrote in article
<95a2je$693$1...@nnrp1.deja.com>:

> I'm totally embarrassed about this, but I figured out my mistake.
> Within my instantiations that didn't show up, I had a signal called
> TPN which was a std_logic_vector. I was ignoring them for the
> testbench and so I had

> TPN => (others <= '0'),

FYI, in this context, "<=" is "less than or equals", so apparently the
compiler was interpreting this as a parenthesized expression.

However, the fact that you did not get an error (if, in fact, you did
not get an error) indicates that your tool did not perform at least
two error checks:

1. "others", being a reserved word, cannot be the name of anything
that can serve as an operand to an expression.

2. Unless you have an overloaded <= operator that returns the type of
TPN (presumably a vector), the tool did not do an adequate job of type
checking this association element (since it was trying to associate a
Boolean value with a vector interface element).

I mention this only because you may wish to report this to your
vendor. If these are, indeed, errors, and they do fix them, the
future users making the same mistake will get at least *some* errors.

Regards,

Paul

--
Paul Menchini | "There must have been a time, probably somewhere near
Menchini & Associates | the beginning, when we could have said 'no.'"
www.mench.com | -- from "Rosencrantz and Guildenstern are Dead"

[Stanislaw Dabek]

Indeed, this bug exists in Active HDL 4.1. Compiler should report syntax
error.

It has been fixed in Active HDL 4.2

Regards,
Stanislaw Dabek