"Don't Cares" in VHDL
Nha D. Vu
in VHDL and simulating. What I'm coding is an address decoder
which looks something looks like:
case address(31 downto 0) is
when "101100001111-------------------" => ...
when "1000001------------------------" => ...
when "10001---------------100001-----" => ...
when others =>
end case;
However, when I simulate (I'm using Synopsys Vhdlsim 3.3b
and Vantage Optium 5.2), and an address which *should* match
(for example, address="1000001000000000000000000000000" should
match with the second case statemen) *does not*!
When I *explicitly* add the don't cares in the testbench, e.g.
address="1000001-----------------------", it simulates OK, but
this seems kind of ridiculous. Shouldn't the simulators
be able to decode valid addresses!?!?
Any help greatly appreciated.
- Dai Vu
--
===========================================================================
N. Dai Vu | "...Education is an admirable thing, but...
n...@motown.ge.com | nothing that is worth knowing can be taught..."
Lockheed Martin |
Moorestown, NJ | - Oscar Wilde
===========================================================================
Sashi Obilisetty
>I'm having problems using the "Don't Care" value
>in VHDL and simulating. What I'm coding is an address decoder
>which looks something looks like:
>
>case address(31 downto 0) is
> when "101100001111-------------------" => ...
> when "1000001------------------------" => ...
> when "10001---------------100001-----" => ...
> when others =>
>end case;
>
>However, when I simulate (I'm using Synopsys Vhdlsim 3.3b
>and Vantage Optium 5.2), and an address which *should* match
>(for example, address="1000001000000000000000000000000" should
>match with the second case statemen) *does not*!
>
>When I *explicitly* add the don't cares in the testbench, e.g.
>address="1000001-----------------------", it simulates OK, but
>this seems kind of ridiculous. Shouldn't the simulators
>be able to decode valid addresses!?!?
>
>Any help greatly appreciated.
>
>- Dai Vu
VHDL tools check equivalence by comparing strings; therefore, the
only string that will match "001" is "001".
That explains why the change you made in the testbench went thru.
Hope this helps,
--
* Sashi Obilisetty *
* Alternative System Concepts, Inc. *
* PO Box 128 Windham NH 03087 *
* tel (603) 437-2234 fax (603) 437-ASC2 URL http://www.ascinc.com *
Jacques Rouillard
n...@gradin.cis.upenn.edu (Nha D. Vu) writes:
> I'm having problems using the "Don't Care" value
> in VHDL and simulating. What I'm coding is an address decoder
> which looks something looks like:
>
> case address(31 downto 0) is
> when "101100001111-------------------" => ...
> when "1000001------------------------" => ...
> when "10001---------------100001-----" => ...
> when others =>
> end case;
>
> However, when I simulate (I'm using Synopsys Vhdlsim 3.3b
> and Vantage Optium 5.2), and an address which *should* match
> (for example, address="1000001000000000000000000000000" should
> match with the second case statemen) *does not*!
The problem is general in VHDL: the names given to the states (be it X, Z,
don't care, even 0 and 1) have only the meaning brought by the subprograms
of the package that defines the type. For example, 0 is 0 only because of
the way "and", "or", etc, are written. Z is 'high impedance' and X is
'conflict' only because of the way the package, and particularly the
resolution function is written.
As for the 'dont care', it has no particular meaning for simulation, and
the STD_LOGIC package does not provide any semantics for it: it's a normal
state. Symetrically, X has no particular meaning in synthesis.
But maybe you're more interested in a solution ?
if match(address(31 downto 0),"101100001111-------------------") then ....
elsif match(address(31 downto 0),"1000001------------------------") then
...
elsif match(address(31 downto 0),"10001---------------100001-----") then
...
end if;
where the function 'match' is something like:
function match(left,right:std_logic_vector) return boolean is
alias aright:std_logic_vector(left'range) is right; -- normalization
begin
for i in left'range loop
if (left(i)/=aright(i)) and (aright(i)/='-') then
return false;
end if;
end loop;
return true;
end;
another one, maybe faster, with a case:
case match_case(address(31 downto 0),
("101100001111-------------------",
"1000001------------------------",
"10001---------------100001-----"
)
) is
when 0=>
when 1=>
when 2=>
when others => null;
end case;
where 'match_case' is something like:
type array_std_logic_vector is array(integer range <>) of
std_logic_vector(31 downto 0);
function match_case(left:std_logic_vector; right:array_std_logic_vector)
return natural;
the body:
function match_case(left:std_logic_vector; right:array_std_logic_vector)
return natural is
alias aleft:std_logic_vector(31 downto 0) is left;
alias aright:array_std_logic_vector(right'low to right'high) is right;
type BOO is array(aright'range) of boolean;
variable tst:BOO:=(others=>true);
variable result : integer := aright'low-1;
begin
for i in aleft'range loop
for j in aright'range loop
if tst(j) then
if (aleft(i)/=aright(j)(i)) and (aright(j)(i)/='-') then
tst(j):=false; end if;
end if;
end loop;
end loop;
for j in aright'range loop
if tst(j) then
assert result = aright'low-1 report "Conflict in match_case"
severity error ;
result := j;
end if;
end loop;
return result - aright'low;
-- returns -1 if no match, otherwise the rank in the array of
bit_vectors.
end;
Of course, all this seems to compile but is untested !!
-- Jacques Rouillard
USA http://vhdl.org/~rouillard EU http://ismea.imt-mrs.fr/~rouillar
Emil Blaschek
Eg. a vector of mvl can have the states '0','1','U','Z'
In the Library there is a teuth-Table defined for each operator,
for each type of type.
the Compiler makes first an "=" operation of of each element of the vector,
where the result is a vector of boolean. if each element of this vector is true,
the result of the comparison is true.
if you want an other behaviour, "overload the opreation".
EB. from Vienna
Dennis McCrohan
>In article <4entsq$r...@netnews.upenn.edu>
>n...@gradin.cis.upenn.edu (Nha D. Vu) writes:
>
>> I'm having problems using the "Don't Care" value
>> in VHDL and simulating. What I'm coding is an address decoder
>> which looks something looks like:
>>
>> case address(31 downto 0) is
>> when "101100001111-------------------" => ...
>> when "1000001------------------------" => ...
>> when "10001---------------100001-----" => ...
>> when others =>
>> end case;
>>
>> However, when I simulate (I'm using Synopsys Vhdlsim 3.3b
>> and Vantage Optium 5.2), and an address which *should*
.bandwidth filter cuts in...
Anyway, what the previous poster has said is entirely correct,
i.e.,the 1164 group didn't define any special semantics for
'-', therefore making it more or less useless, unless you
define all your own functions (mainly relational ops) that
understand it. I have heard that the IEEE synthesis working
group also basically punted on this issue. Specifically, that
the NUM_STD package basically gave '-' the same semantics as
'0' for relational operators.
Anybody have more details on this? Like what was their
rationale?
-dm
Kalpesh Patel
>
> I'm having problems using the "Don't Care" value
> in VHDL and simulating. What I'm coding is an address decoder
> which looks something looks like:
>
> case address(31 downto 0) is
> when "101100001111-------------------" => ...
> when "1000001------------------------" => ...
> when "10001---------------100001-----" => ...
> when others =>
> end case;
>
> However, when I simulate (I'm using Synopsys Vhdlsim 3.3b
> (for example, address="1000001000000000000000000000000" should
> match with the second case statemen) *does not*!
>
> address="1000001-----------------------", it simulates OK, but
> this seems kind of ridiculous. Shouldn't the simulators
> be able to decode valid addresses!?!?
>
> Any help greatly appreciated.
>
> - Dai Vu
>
> ===========================================================================
> N. Dai Vu | "...Education is an admirable thing, but...
> n...@motown.ge.com | nothing that is worth knowing can be taught..."
> Lockheed Martin |
> Moorestown, NJ | - Oscar Wilde
> ===========================================================================
You are confusing the difference between a simulation state (don't care state) versus don't care function. In VHDL there are nine discrete
states for a signal, they are :
U - Unitialized
X - Forcing Unknown
0 - Forcing 0
1 - Forcing 1
Z - High Impedance
W - Weak Unknown
L - Weak 0
H - Weak 1 and
- - Don't care
In VHDL don't care means '-' state, not 'U' or '1' or anything else. In simulation you are trying to propegate don't care through the
design and as a result of it you want to see '-' at the output so you know that that node is going to uknown state. If simulator replace it
with any state other than don't care '-', then you will not know where the don't care state propegated from.
To put it simply, in you case statement, you must handle 9 to the power of 31 cases in the case statement. For the purposes of simulation,
"...0000" is one state, "...0001" is another state, "...000x" is another state, etc...
You case statement will end up as follows:
case address(31 downto 0) is
when "101100001111UUUUUUUUUUUUUUUUUUU" |
"101100001111UUUUUUUUUUUUUUUUUUX" |
"101100001111UUUUUUUUUUUUUUUUUU0" |
"101100001111UUUUUUUUUUUUUUUUUU1" |
"101100001111UUUUUUUUUUUUUUUUUUZ" |
"101100001111UUUUUUUUUUUUUUUUUUW" |
"101100001111UUUUUUUUUUUUUUUUUUL" |
"101100001111UUUUUUUUUUUUUUUUUUH" |
"101100001111UUUUUUUUUUUUUUUUUU-" |
"101100001111UUUUUUUUUUUUUUUUUXU" |
"101100001111UUUUUUUUUUUUUUUUUXX" |
"101100001111UUUUUUUUUUUUUUUUUX0" |
"101100001111UUUUUUUUUUUUUUUUUX1" |
"101100001111UUUUUUUUUUUUUUUUUXZ" |
"101100001111UUUUUUUUUUUUUUUUUXW" |
"101100001111UUUUUUUUUUUUUUUUUXL" |
"101100001111UUUUUUUUUUUUUUUUUXH" |
"101100001111UUUUUUUUUUUUUUUUUX-" |
.
.
.
"101100001111-------------------" => ...
when "1000001UUUUUUUUUUUUUUUUUUUUUUUU" |
.
.
.
"1000001------------------------" => ...
when "10001UUUUUUUUUUUUUUU100001UUUUU" |
.
.
.
"10001---------------100001-----" => ...
when others =>
end case;
So you are looking at 9 to the 30th (if I counted the width of the bus correctly) power different states on the bus!
--
.
_| _/ _|_|_|_| \_|_/
_| _/ _| _| ______________.ooO__(_o o_)___Ooo.______________
_| _/ _| _| (_)
_| _/ _| _|
_| _/_\ _|_|_|_| Kalpesh Patel | Symbol Technology
_|_/ _\ _| (516) 563-2400 @3292 | 116 Wilbur Place, B3
_| _\ _| kalp...@symbol.com | Bohemia, NY 11716
_| _\ _|
_| _\ _| .ooO Ooo.
______________________________________\ (_________) /__________________
\_) (_/
Kalpesh Patel
>
> In article <4entsq$r...@netnews.upenn.edu>
> n...@gradin.cis.upenn.edu (Nha D. Vu) writes:
>
> > in VHDL and simulating. What I'm coding is an address decoder
> > which looks something looks like:
> >
> > case address(31 downto 0) is
> > when "101100001111-------------------" => ...
> > when "1000001------------------------" => ...
> > when "10001---------------100001-----" => ...
> > when others =>
> > end case;
> >
> > However, when I simulate (I'm using Synopsys Vhdlsim 3.3b
> > and Vantage Optium 5.2), and an address which *should* match
> > (for example, address="1000001000000000000000000000000" should
> > match with the second case statemen) *does not*!
>
I think what he may be looking for is following:
If ("101100001111" = address (30 downto 19))
Then ...
Elsif ("1000001" = address (30 downto 24))
Then ...
Elsif ("10001" = address (30 downto 26) and "100001" = address (10 downto 5))
Then ...
Else ...
End if;
"10001---------------100001-----"
pell...@seanet.com
>Anyway, what the previous poster has said is entirely correct,
>i.e.,the 1164 group didn't define any special semantics for
>'-', therefore making it more or less useless, unless you
>define all your own functions (mainly relational ops) that
>understand it. I have heard that the IEEE synthesis working
>group also basically punted on this issue. Specifically, that
>the NUM_STD package basically gave '-' the same semantics as
>'0' for relational operators.
I would not go so far as say that 1164 was useless... but it
would have been nice if this had been addressed at that time
1164 was released. It appears to me that the problem is solved
with the introduction of standard 1076.3, which gives us
the STD_MATCH functions for just this purpose. STD_MATCH turns
the '-' character into a true don't-care. (But do the synthesis
vendors see it as a logical don't-care yet?? Nyah...)
-- DaveP
-- David Pellerin --------------------------------- pell...@seanet.com --
-- Accolade Design Automation, Inc. ---------- (206) 788-3768 Voice/FAX --
-- 26331 NE Valley, #5-120 ---------- (206) 972-6020 Voicemail/Cellular --
-- Duvall, WA 98019 ---------------------------- http://www.acc-eda.com --
Frank Guerino
writes:
>
>I'm having problems using the "Don't Care" value
>in VHDL and simulating. What I'm coding is an address decoder
>which looks something looks like:
>
>case address(31 downto 0) is
> when "101100001111-------------------" => ...
> when "1000001------------------------" => ...
> when "10001---------------100001-----" => ...
> when others =>
>end case;
>
>However, when I simulate (I'm using Synopsys Vhdlsim 3.3b
>and Vantage Optium 5.2), and an address which *should* match
>(for example, address="1000001000000000000000000000000" should
>match with the second case statemen) *does not*!
>
>address="1000001-----------------------", it simulates OK, but
>this seems kind of ridiculous. Shouldn't the simulators
>be able to decode valid addresses!?!?
>
Hi Dai,
I had this same problem. It turns out you usually have
to build your own state resolvers if you don't have packages
that already do this for you.
FG
David Bishop x66788
>roui...@acm.org (Jacques Rouillard) wrote:
>>n...@gradin.cis.upenn.edu (Nha D. Vu) writes:
>>
>>> I'm having problems using the "Don't Care" value
>>> in VHDL and simulating. What I'm coding is an address decoder
>>> which looks something looks like:
>>>
>>> case address(31 downto 0) is
>>> when "101100001111-------------------" => ...
>>> when "1000001------------------------" => ...
>>> when "10001---------------100001-----" => ...
>>> when others =>
>>> end case;
>>>
>>> However, when I simulate (I'm using Synopsys Vhdlsim 3.3b
>>> and Vantage Optium 5.2), and an address which *should*
>rationale?
Actually, we wrote it into the IEEE Synthesis spec (1076.3)
Take a look at http://vhdl.org/vi/vhdlsynth/vhdlsynth.html
Download the "numeric_std.vhd".
Look at "std_match". This function call will do what you want.
Now that 1076.3 has passed Ballot, we should start seeing vendors adding
it to their IEEE libraries. Exemplar Logic already has.
---
David Bishop
INTERNET: bis...@dtc.kodak.com | The opinions voiced are mine
US MAIL: 1194 West Ave, Hilton NY 14468 | and not my company's.
PHYSICAL: 43:17:17N 77:47:37E 281' |