On Thursday, October 22, 2020 at 4:08:51 PM UTC-4, Jim Lewis wrote:
> Can you post a minimum example that can be pasted into a file and independently tested?
Sure, this has been hashed out in stackexchange to the point I'm pretty convinced it is a simulator bug. It works on Modelsim and ghdl or if very minor changes are made to the code as noted in the comments.
I use 4 space tabs. Google shouldn't wrap the lines but your reader might.
It will be interesting to find that it is my code and not a bug.
-- Test synthesis of counters and carry out flags
-- use work.Common.all;
entity VHDL_test is
CLK_HZ : REAL := 33.554432E6 );
-- Clk : in std_logic := '1';
Cnt_En : in std_logic := '1';
Test_Out_a : out std_logic;
Carry_Out_a : out std_logic
architecture TB_ARCH of VHDL_test is
constant Clock_Half_Period : time := 500 ms / CLK_HZ; -- 14901 ps;
constant Cntr_Width : positive := 8;
constant Cntr_Modulus : positive := 2**Cntr_Width;
constant One_uns : unsigned(Cntr_Width downto 0) := "000000001";
signal Clk : std_logic := '1';
signal Count_a, nxt_cnt_a : unsigned(Cntr_Width - 1 downto 0) := (others => '0');
Clk_gen: Clk <= not Clk after Clock_Half_Period; -- comment out for synth
(Carry_Out_a, nxt_cnt_a) <= RESIZE(Count_a, nxt_cnt_a'length + 1) - 1; -- fails
-- (Carry_Out_a, nxt_cnt_a) <= RESIZE(Count_a, nxt_cnt_a'length + 1) - One_uns; -- works
-- (Carry_Out_a, nxt_cnt_a) <= ("0" & Count_a) - 1; -- works
test_ag: process (Clk) is
if rising_edge(Clk) then
Test_Out_a <= Carry_Out_a;
if (Cnt_En OR not Carry_Out_a) then
Count_a <= nxt_cnt_a;
end process test_ag;
end TB_ARCH; -- VHDL_test
-- Get 1,500 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209