Graphical toplevel assembly
Jos De Laender
I'm looking for information about tools that allow to assemble
VHDL toplevels in a graphical way.
The tool should
- allow graphical editing of blocks
- keep synchronization between the textual vhdl behind
it and the graphical presentation, i.e. if graphics
change, text must follow and vice-versa.
- really support VHDL, i.e. it should work also with constructs
that are not in Verilog such as records.
Thanks for any information.
--
Jos De Laender | mailto:jd...@sh.bel.alcatel.be
Alcatel - SSD |
ASIC design - VA21 |
F. Wellesplein 1 | Phone : (32)(0) 3 240 74 61
B-2018 Antwerp, Belgium | Fax : (32)(0) 3 240 99 47
Jos Dreesen
>
> Hi,
>
> I'm looking for information about tools that allow to assemble
> VHDL toplevels in a graphical way.
>
> The tool should
>
>
>B) - keep synchronization between the textual vhdl behind
> it and the graphical presentation, i.e. if graphics
> change, text must follow and vice-versa.
>
> that are not in Verilog such as records.
The first two were possible with the Speedchart tool, but the company
that
provided this tool has collapsed...
Also Cadence 97A a.k.a as Cadence 4.4.1 has this possibility, I've just
used a ideal combination ( for my purpose) of VHDL and schematics
for a mixed-mode IC design.
I don't know of any tool that does "C" ......
Regards,
Jos Dreesen
--
Jos Dreesen Email <j.dr...@zrh.sc.philips.com>
Philips Semiconductors Tel + 41 1 465 11 62 Fax + 41 1 465 18 06
CH-8045 Zurich Private : tel/fax + 41 1 722 29 05
Bob Myers
block diagrams, VHDL text, state machines, etc. -- and can generate
a "flat" hdl file that can be used by other synthesis tools (such
as Exemplar's Leonardo). Also, it has versioning control as an
option...
I believe their web site is www.summit-design.com
-Regards,
Bob
In article <35D183...@sh.bel.alcatel.be>, jd...@sh.bel.alcatel.be says...
>
>Hi,
>
>I'm looking for information about tools that allow to assemble
>VHDL toplevels in a graphical way.
>
>The tool should
>
> - allow graphical editing of blocks
>
> - keep synchronization between the textual vhdl behind
> it and the graphical presentation, i.e. if graphics
> change, text must follow and vice-versa.
>
> - really support VHDL, i.e. it should work also with constructs
> that are not in Verilog such as records.
>
Scherer Anton
>
> Hi,
>
> I'm looking for information about tools that allow to assemble
> VHDL toplevels in a graphical way.
graphics from VHDL-files. Have a look at http://www.mentorg.com
Since I start my design with graphical top-down I never used it.
Regards,
Anton
Nigel Elliot
Jos De Laender wrote:
> Hi,
>
> I'm looking for information about tools that allow to assemble
> VHDL toplevels in a graphical way.
>
> The tool should
>
> - allow graphical editing of blocks
>
> - keep synchronization between the textual vhdl behind
> it and the graphical presentation, i.e. if graphics
> change, text must follow and vice-versa.
>
> - really support VHDL, i.e. it should work also with constructs
> that are not in Verilog such as records.
>
> Thanks for any information.
>
> --
> Jos De Laender | mailto:jd...@sh.bel.alcatel.be
> Alcatel - SSD |
> ASIC design - VA21 |
> F. Wellesplein 1 | Phone : (32)(0) 3 240 74 61
> B-2018 Antwerp, Belgium | Fax : (32)(0) 3 240 99 47
>
> http://www.sh.bel.alcatel.be/users/jdla/html/Home.html
Jos,
Mentor Graphics provide a tool that can do all of the above, called
Renoir.You can get a demo version from our web page at
http://www.mentorg.com/renoir/index.html
regards
- Nigel
Sorry
The link is
David R Brooks
:Jos De Laender wrote:
:> I'm looking for information about tools that allow to assemble
:> VHDL toplevels in a graphical way.
:renoir (Mentor Graphics) has a tool for it. It allows generating
:graphics from VHDL-files. Have a look at http://www.mentorg.com
:Since I start my design with graphical top-down I never used it.
:
However, Renoir is quite costly. Specifically, in $A, purchase about
$A9500, annual maintenance about $A1500.
-- Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key via <http://www.iinet.net.au/~daveb/crypto.html>, or servers
asa...@my-dejanews.com
> >
> > I'm looking for information about tools that allow to assemble
> > VHDL toplevels in a graphical way.
> renoir (Mentor Graphics) has a tool for it. It allows generating
> graphics from VHDL-files. Have a look at http://www.mentorg.com
> Since I start my design with graphical top-down I never used it.
You could also take a look at Visual-HDL from summit design http://www.sd.com
and VeriBest http://www.veribest.com do an integrated VHDL and PCB design
tool, obviously you can only purchase the vhdl section if thats all you want.
They both offer simmilar features to renoir and both at equally silly prices.
Andrew
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Mark Hampton
software is another question. The approach taken would seem to be more
comprehensive than any commercial offerings I've seen.
http://www-itiv.etec.uni-karlsruhe.de/FORSCHUNG/f_vse/vyper.html
--
Mark Hampton
Project Engineer
Silicon Systems Limited
32 - 34 Harcourt Street, Dublin, Ireland
Ph: 00 353 1 402 5728
Fax: 00 353 1 402 5711
Email: mham...@ssd.ie
Steve Bird
Steve...
In article <35D183...@sh.bel.alcatel.be>, Jos De Laender
<jd...@sh.bel.alcatel.be> writes
>Hi,
>
>I'm looking for information about tools that allow to assemble
>VHDL toplevels in a graphical way.
>