need vhdl code for 16 bit serial-in, serial-out shift register

[Mohamed Daffe]

i need a vhdl code for 16 bit serial-in, serial-out shift register

[Spam Hater]

Serial in, serial out?

How about:

out <= in;

I think you wanted to ask a different question.

SH7

[M Pedley]

A 16 bit fifo??

[Niv]

How about (but ignore syntax just a very quick stab at it);

ENTITY shift_register IS
PORT (clock IN;
ser_in IN;
ser_out OUT);
END shift register;

ARCHITECTURE rtl OF shift_register IS

SIGNAL shiftreg STD_LOGIC_VECTOR(15 DOWNTO 0);

BEGIN -- Architecture

ser_out <= shiftreg(0); -- Shift bit out.

shifter : PROCESS (clock)
BEGIN
IF rising_edge(clock) THEN
IF reset THEN
-- sync reset stuff here, i.e. shiftreg <= (OTHERS => '0');
ELSE
shift_reg <= ser_in & shiftreg(15 DOWNTO 1); -- Shift into top bit.
END IF;
END IF;
END PROCESS;

END rtl;

"Mohamed Daffe" <mda...@triad.rr.com> wrote in message
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