STD_LOGIC_VECTOR to STRING
Narcis Simon
Hi,
anyone knows how to convert from std_logic_vector to string?
All I want is to join the converted numbered with other literal
strings to add them in an assert statement.
Thanks.
Narcis Simon i Rabasseda
Centre Nacional de Microelectronica
Bellatera, Catalunya, Europa
Bert Cuzeau
I suggest the following solutions :
1. probably easiest for use in transcripts, see example below :
---- this example displays an Integer value in a transcript message
for instance in 0 to 1 loop
assert false
report "Initializing device " & integer'image(instance)
severity note;
etc...
-------
2. Use write /writeline as in extract below :
----- this is part of an Abel Test Vector Generator (c) Synario Design
Automation
----- part of the design examples included in SYnario.
procedure write_vectors (oe, clr : in std_logic;
q : in std_logic_vector) is
variable myline : line;
variable clock_string : string(1 to 5) := "[.c.,";
variable comma_string : string(1 to 2) := ", ";
variable mid_string : string(1 to 6) := "] -> [";
variable end_string : string(1 to 2) := "];";
variable hex_string : string(1 to 2) := "^h";
begin
write(myline, clock_string);
write(myline, oe);
write(myline, comma_string);
write(myline, clr);
write(myline, mid_string);
for i in q'high downto 1 loop
write(myline, q(i));
write(myline, comma_string);
end loop;
write(myline, q(0));
write(myline, end_string);
writeline(vecfile, myline);
end write_vectors;
procedure write_vectors (dir : in std_logic;
a_ext, b_ext, a, b : in std_logic_vector) is
variable myline : line;
variable clock_string : string(1 to 2) := "[ ";
variable comma_string : string(1 to 2) := ", ";
variable mid_string : string(1 to 6) := "] -> [";
variable end_string : string(1 to 2) := "];";
variable hex_string : string(1 to 2) := "^h";
begin
write(myline, clock_string);
for i in a_ext'high downto 0 loop
write(myline, a_ext(i));
write(myline, comma_string);
end loop;
for i in b_ext'high downto 0 loop
write(myline, b_ext(i));
write(myline, comma_string);
end loop;
write(myline, dir);
write(myline, mid_string);
for i in a'high downto 0 loop
write(myline, a(i));
write(myline, comma_string);
end loop;
for i in b'high downto 1 loop
write(myline, b(i));
write(myline, comma_string);
end loop;
write(myline, b(0));
write(myline, end_string);
writeline(vecfile, myline);
end write_vectors;
-----
Don't forget that you'll need indeed the textio library declared as in :
library ieee;
library stdtxtio;
use std.textio.all;
use ieee.std_logic_1164.all;
use stdtxtio.std_logic_textio.all;
-- etc...
Hope this helps,
Regards,
Examples courtesy Data I/O - Synario Design Automation - The Makers of
SYNARIO (tm)
//////////////////////////////////////////////////////
Bert CUZEAU - ALSE France
* FPGA-CPLD Design and Synario Expert
* VHDL and Synario Trainings
* Consultant
http://ourworld.compuserve.com/homepages/alse
Return address is invalid to defeat junk mail.
Please reply to : alse@compuserve and add ".com".
//////////////////////////////////////////////////////
Narcis Simon <si...@cnm.es> wrote in article <32D3C343...@cnm.es>...
Ben Cohen
si...@cnm.es wrote:
>anyone knows how to convert from std_logic_vector to string?
>All I want is to join the converted numbered with other literal
>strings to add them in an assert statement.
Take a look at the image package extracted from the book
"VHDL Answers to Frequently Asked Questions" and posted on my web site
in file image_pb.vhd. It does what you need.
-----------------------------------------------------------
-- Ben Cohen, Hughes Aircraft Co, RE- R1/B507
-- ** "VHDL Coding Styles and Methodologies",
-- ISBN 0-7923-9598-0 Kluwer Academic Publishers, 1995
-- ** "VHDL Answers to Frequently Asked Questions"
-- ISBN 0-7923-9791-6 Kluwer Academic Publishers, 1997
-- FTP site: users.aol.com /vhdlcohen/vhdl
-- Web page: http://members.aol.com/vhdlcohen/vhdl
-- (310) 334-7389, fax: (310) 334-1749
-----------------------------------------------------------
Andrew Rushton
> Narcis Simon <si...@cnm.es> wrote in article <32D3C343...@cnm.es>...
> > Hi,
> > anyone knows how to convert from std_logic_vector to string?
> > All I want is to join the converted numbered with other literal
> > strings to add them in an assert statement.
> > Thanks.
I missed the original post, so here's a rather late response...
Here's the function I use for std_logic_vector to string conversion:
function to_string (arg : std_logic_vector) return string is
variable result : string (1 to arg'length);
variable v : std_logic_vector (result'range) := arg;
begin
for i in result'range loop
case v(i) is
when 'U' =>
result(i) := 'U';
when 'X' =>
result(i) := 'X';
when '0' =>
result(i) := '0';
when '1' =>
result(i) := '1';
when 'Z' =>
result(i) := 'Z';
when 'W' =>
result(i) := 'W';
when 'L' =>
result(i) := 'L';
when 'H' =>
result(i) := 'H';
when '-' =>
result(i) := '-';
end case;
end loop;
return result;
end;
Note that in VHDL'93 you can just use the 'imager attribute:
std_logic_vector'image(arg)
The first solution works in both '87 or '93 versions.
-- __ ____ ____ ____ ____ __
__/\_\ /_/\_\/_/\_\/_/\_\/_/\_\ /_/\__
__/\_\/_/ /\_\/_/\_\/_/\_\/_/\_\/_/\ \_\/_/\__
/\_\/_/\_\ \/_/ Andy Rushton \_\/ /_/\_\/_/\
\/_/\_\/_/ /\ \ a...@transeda.com / /\ \_\/_/\_\/
\/_/\_\ \/_/\_\/_/\_\/_/\_\/_/\_\/ /_/\_\/
\/_/ \_\/_/\_\/_/\_\/_/\_\/_/ \_\/
http://www.transeda.com/interest/ar/
------- End of forwarded message -------
Ben Cohen
>>Note that in VHDL'93 you can just use the 'imager attribute:
>> std_logic_vector'image(arg)
That does not work!. The image attribute requires a scalar prefix.
with MTI's compiler:
...
signal RegA_s : Std_Logic_Vector(31 downto 0);
begin
assert false
report std_logic_vector'image(RegA_s)
severity note;
...
# ERROR: C:/BEN/BKPLUS/TIMAGE.VHD(90): Attribute image requires a scalar prefix
Check my web site for the image package that declared the overloaded image function.
Those functions make use of the Std_Logic_TextIO package.
The package declaration is as follows:
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_TextIO.all;
use IEEE.Std_Logic_Arith.all;
library Std;
use STD.TextIO.all;
package Image_Pkg is
function Image(In_Image : Time) return String;
function Image(In_Image : Bit) return String;
function Image(In_Image : Bit_Vector) return String;
function Image(In_Image : Integer) return String;
function Image(In_Image : Real) return String;
function Image(In_Image : Std_uLogic) return String;
function Image(In_Image : Std_uLogic_Vector) return String;
function Image(In_Image : Std_Logic_Vector) return String;
function Image(In_Image : Signed) return String;
function Image(In_Image : UnSigned) return String;
end Image_Pkg;
Wolfgang Ecker
Ben Cohen Wrote:
---------------------------------------------------------------------------------
>>Note that in VHDL'93 you can just use the 'imager attribute:
>> std_logic_vector'image(arg)
That does not work!. The image attribute requires a scalar prefix.
with MTI's compiler:
...
signal RegA_s : Std_Logic_Vector(31 downto 0);
begin
assert false
report std_logic_vector'image(RegA_s)
severity note;
...
# ERROR: C:/BEN/BKPLUS/TIMAGE.VHD(90): Attribute image requires a scalar prefix
Check my web site for the image package that declared the overloaded image function.
Those functions make use of the Std_Logic_TextIO package.
^^^^^^^^^^^^^^^^^^^^^^^^^
--------------------------------------------------------------------------------------
We uset the package from Ben Cohen for some time but we were forced to rewrite it.
Some simulators crashed non-deterministically after about half an hour simulation
time. Evaluating this problem showed that these tools did not process garbage collection
in conjunction with dynamically allocated memory correctly.
Wolfgang
Andrew Rushton
Ben Cohen <Vhdl...@aol.com> writes:
> >>Note that in VHDL'93 you can just use the 'imager attribute:
> >> std_logic_vector'image(arg)
>
> That does not work!. The image attribute requires a scalar prefix.
> with MTI's compiler:
Whoops! This is true - it just goes to show how little VHDL'93 I've
written compared with VHDL'87.
> Check my web site for the image package that declared the overloaded image function.
> Those functions make use of the Std_Logic_TextIO package.
Snap! I have some versions on my Web site too! There is source code
for most of them on
http://www.transeda.com/interest/ar/print_values.html
These do not rely on any other package.
There is also source code for std_logic_textio, numeric_bit_textio and
numeric_std_textio. See:
http://www.transeda.com/interest/ar/
--
\0/ \0/ \ \ / / \0/ \0/
| / /) | (\ \ |
__/ \___/\___/0\___/0\___/0\___/\___/ \__
Andy Rushton - TransEDA Limited UK
a...@transeda.com - http://www.transeda.com/interest/ar/
Ben Cohen
ec...@zfe.siemens.de (Wolfgang) wrote:
>We used the package from Ben Cohen for some time but we were forced to rewrite it.
>Some simulators crashed non-deterministically after about half an hour simulation
>time. Evaluating this problem showed that these tools did not process garbage >collection in conjunction with dynamically allocated memory correctly.
For the record, the functions declared in my "image" package do make use of the
Std_Logic_TextIO package (as mentioned before). However, the image functions do
retrieve any dynamically allocated memory thru the "deallocate" statement. As you
mentioned, the problem is in the simulator tools.
Would you please share with us the names of these simulation tools and vendors?
Have you contacted them about this problem? Also, have you experienced other similar
problems with access types?
Thanks,