synthesis definition?
toto
What is the definition and difference of
1.RTL synthesis,
2.Behavioural synthesis
3.System level synthesis
Is there a good website I can study a little bit?
Thanks.
toto
Marek Ponca
with utilizing the Designware components for Altera FLEX devices
in FPGA Compiler II ?
How can apropriate architecture be manualy chosen ?
(e.g. for add_sub - rpl/cla/bk/clf ...)
Or does the tool do it automatically ?
Marek
--
Marek Ponca
Ilmenau Technical University
Germany
Marek Ponca
Mike Treseler
> A newbie's stupid question:
Sounds more like an old textbook's stupid question.
You might have to read it to see what
the author had it mind, but here's my definitions:
> What is the definition and difference of
> 1.RTL synthesis,
HDL code that will synthesize with most any CAE tool.
> 2.Behavioural synthesis
HDL code that will synthesize with the latest
rev of my tools.
> 3.System level synthesis
HDL code that will fit in a single device and
replace a 5 year old circuit board.
> Is there a good website I can study a little bit?
Volker Hetzer
>
> toto wrote:
> > 3.System level synthesis
>
> HDL code that will fit in a single device and
> replace a 5 year old circuit board.
supposedly available in three years.
Greetings!
Volker
--
They laughed at Galileo. They laughed at Copernicus. They laughed at
Columbus. But remember, they also laughed at Bozo the Clown.
Tom Kaminski
- RTL code can be synthesized.
- Behavioural code cannot be synthesized.
VHDL was originally designed to model the behaviour of digital circuits. It
was not originally intended to be used for synthesis (ie. creating
netlist ). As a result, the VHDL language contains many features that
cannot be represented in actual hardware such as a delay (i.e. wait for 6
ns; ) For the purpose of synthesis using VHDL, only a subset of the
language can be used. VHDL code written using this subset (exclusively) is
called RTL code, otherwise it is Behavioural code.
I use Behavioural modelling for testbenches because testbenches do not need
to be synthesized (and it is a lot easier to code too).
Regards,
Tom Kaminski
toto <xy_...@yahoo.com> wrote in message
news:9ajejh$om0$1...@cnn.Princeton.EDU...
Paul Hands
This isn't a stupid question - you have to start somewhere!
My 2c worth................
RTL Synthesis.
The acronym RTL tells you most of what you need to know - RTL =
"Register Transfer Level".
Most often in Verilog or VHDL, this a description at the level of the
registers you want in your design and of the data manipulations which
occur between those registers. In other words, the architecture of the
design is already substantially fixed - you've picked the flops and
their clocks and defined what happens to data as it flows between them.
This was the first hardware description language level to be easily
synthesisable, and many thousands of designs have been produced in this
way. In general, RTL code maps well on to real cells in most ASIC type
flows. The drawback is that you have comparatively little flexibility
left when your design is expressed at this level. Changes can require a
complete rewrite of the RTL code.
Behavioural Synthesis.
This is a step up in abstraction level when describing your design.
Instead of specifying exactly what flops exist and what happens between
them, you can write a much simpler description of the required
functionality - much like writing an algorithm in C. It's much easier
to write and simulate behavioural code, but a synthesis tool has to
figure out how the clocking should work and how to schedule data
manipulations so that it can produce something which maps well on to a
real technology. Some, but not all behavioural descriptions can be
synthesized, and there are commercial tools on the market which (at
least partially) address this level of abstraction. VHDL, for example,
allows you to write behaviour which can not be synthesized. File
handling is one example - very useful in testbenches, but can not imply
a structure expressed in gates and flip flops. In general, the
behavioural synthesis market has not taken off in the way that the RTL
synthesis market did, and this is reflected in the much lower number of
finished designs.
System Level
It is quite often the case that complex systems are evaluated at a very
abstract level - usually C or C++ - by compiling the code which
represents them and running it as an executable program. Once the
system behaviour is correct, the problem is to translate that into
something real. Most complex sytems comprise both hardware and software
and a choice has to be made as to the partitioning. There are some
beginnings in this area right now, but it has a long way to go. As
regards synthesizing a system, I'm not sure anything really exists in
this area, although you may want to look at www.systemc.org.
I hope this helps.
Paul