SRA question

[Felix Augusto Olmedo Ulibarri]

Hello:
I saw the message that Thomas Reinemann posted before, I;m trying to use
some shift funtions
but when I use SRA i get the following error:
No feasible entries for infix op: "sra"
I'm using VCOM, and I also tried the SLL and SRL functions, it worked
fine, but I can't get the SRA
function to work.
The code I'm using is:
shift_count_value<=unsigned(shift_count);
result <=std_logic_vector(unsigned(a) sra
to_integer(shift_count_value));

where
shift_count_value is unsigned(4 downto 0)
shift_count is std_logic_vector(4 downto 0)
a is std_logic_vector(31 downto 0)
and result is also a 32-bit std_logic_vector

Regards

felix olmedo

[Srinivasan Venkataramanan]

Hi,
The problem here is that the "Arithmetic Shift" operators are NOT
OVERLOADED by the numeric_std package - I am surprised by this fact!
Actually I am not quite sure about this, this is what I see from
ModelSim & VHDLSimli - I don't have the authentic version from IEEE).
So I wish someone from the VHDL Standardisation committe elobartes this
further.

Can someone please try with Cadence tools and see if they accept it? -
TIA.

Looking forward to any more explanation.

Regards,
Srini

In article <3A0A094D...@correo.mty.itesm.mx>,

--
Srinivasan Venkataramanan
ASIC Design Engineer
Chennai, India

Sent via Deja.com http://www.deja.com/
Before you buy.

[Mike Treseler]

Srinivasan Venkataramanan wrote:
>
> Hi,
> The problem here is that the "Arithmetic Shift" operators are NOT
> OVERLOADED by the numeric_std package - I am surprised by this fact!
> Actually I am not quite sure about this, this is what I see from
> ModelSim & VHDLSimli

I can confirm that SLL, SRL, ROL, ROR are overloaded for unsigned
and that SLA, SRA are not touched in ver 2.4 of:

-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_STD)
-- Version: 2.4
-- Date : 12 April 1995

There may be a good reason why, but I don't know it.

-- mike.treseler at flukenetworks dot com

[Felix Olmedo Ulibarri]

Then, how can I implemet a SRA over a std_logic_vector
what´s the best way??

Mike Treseler wrote:

> Srinivasan Venkataramanan wrote:
> >
> > Hi,
> > The problem here is that the "Arithmetic Shift" operators are NOT
> > OVERLOADED by the numeric_std package - I am surprised by this fact!
> > Actually I am not quite sure about this, this is what I see from
> > ModelSim & VHDLSimli
>

[Edwin Naroska]

Hi,

Felix Olmedo Ulibarri wrote:

> Then, how can I implemet a SRA over a std_logic_vector

> what愀 the best way??
>

if the vector represents a signed integer (with the sign at its lefmost
bit position) then you may use function shift_right from package
IEEE.numeric_std:

my_std_logic_vector1 <=
std_logic_vector(shift_right(signed(my_std_logic_vector2), shift_count));

(I hope that "shift_right" will be accepted by your synthesis tool).

--
Edwin

[Jonas Thor]

Hmm.. I've read the other answers to this thread... But isn't the real
meaning of SRA a right shift of a SIGNED type? If you have an unsigned
type you should use SRL instead. SRA "keeps" the sign of a signed
type, but for unsigned I don't understand why SRA should be defined.

/Jonas

On Wed, 08 Nov 2000 20:17:49 -0600, Felix Augusto Olmedo Ulibarri

[J. Bhasker]

It took me a while to track down the reasoning behind this - had to dig
up some old old stuff. This has identified a typo in the
document that describes 1076.3 - the packages are fine. Here goes ....

The Working Group had originally proposed the functions
SHIFT_LEFT, SHIFT_RIGHT, ROTATE_LEFT and ROTATE_RIGHT as the functions
to be used to arithmetic shifts and logical rotates only.

However as part of balloting feedback, a feedback comment was
why not allow the predefined (shift,rotate)
operators to behave the same way as the
above functions since the predefined operators provide a nice
infix notation - better to write "A srl 2" compared to "SHIFT_RIGHT(A,
2)" - and this proposal was accepted.

So sll, srl, rol, ror are overloaded to behave exactly the same as
SHIFT_LEFT, SHIFT_RIGHT, ROTATE_LEFT, ROTATE_RIGHT respectively.
Also these four overloaded operators are defined in both the
NUMERIC_BIT and the NUMERIC_STD packages - the packages have the
correct info. However in the standard document, IEEE Std1076.3-1997,
pg 7, Table 1, For s9-s16 under "NUMERIC_BIT", it says "predefined
in VHDL" which is not correct. It should say exactly the same
as what is in the column for "NUMERIC_STD".

- bhasker

Felix Olmedo Ulibarri wrote:
>
> Then, how can I implemet a SRA over a std_logic_vector
> what愀 the best way??
>

> Mike Treseler wrote:
>
> > Srinivasan Venkataramanan wrote:
> > >

> > > Hi,
> > > The problem here is that the "Arithmetic Shift" operators are NOT
> > > OVERLOADED by the numeric_std package - I am surprised by this fact!
> > > Actually I am not quite sure about this, this is what I see from
> > > ModelSim & VHDLSimli
> >

[Felix Olmedo Ulibarri]

Your information is very interesting and useful. I was not sure of what Mike
wrote before.
I´ve used the original proposed functions, as well as the late proposed
functions (sll, srl), and they worked fine too.
However, I still can't get the job done when I try to use SRA.
I kept working on some other parts of my design, and left this issue to be
solved as soon as I could get more info.
I´d really appreciate any sugestion you could give me to solve this problem.

Again, thanks to all of you four your interest and time dedicated to answer my

original question.

Felix Olmedo

"J. Bhasker" wrote:

> It took me a while to track down the reasoning behind this - had to dig
> up some old old stuff. This has identified a typo in the
> document that describes 1076.3 - the packages are fine. Here goes ....
>
> The Working Group had originally proposed the functions
> SHIFT_LEFT, SHIFT_RIGHT, ROTATE_LEFT and ROTATE_RIGHT as the functions
> to be used to arithmetic shifts and logical rotates only.
>
> However as part of balloting feedback, a feedback comment was
> why not allow the predefined (shift,rotate)
> operators to behave the same way as the
> above functions since the predefined operators provide a nice
> infix notation - better to write "A srl 2" compared to "SHIFT_RIGHT(A,
> 2)" - and this proposal was accepted.
>
> So sll, srl, rol, ror are overloaded to behave exactly the same as
> SHIFT_LEFT, SHIFT_RIGHT, ROTATE_LEFT, ROTATE_RIGHT respectively.
> Also these four overloaded operators are defined in both the
> NUMERIC_BIT and the NUMERIC_STD packages - the packages have the
> correct info. However in the standard document, IEEE Std1076.3-1997,
> pg 7, Table 1, For s9-s16 under "NUMERIC_BIT", it says "predefined
> in VHDL" which is not correct. It should say exactly the same
> as what is in the column for "NUMERIC_STD".
>
> - bhasker
>
> Felix Olmedo Ulibarri wrote:
> >
> > Then, how can I implemet a SRA over a std_logic_vector

> > what´s the best way??

> >
> > Mike Treseler wrote:
> >
> > > Srinivasan Venkataramanan wrote:
> > > >

> > > > Hi,
> > > > The problem here is that the "Arithmetic Shift" operators are NOT
> > > > OVERLOADED by the numeric_std package - I am surprised by this fact!
> > > > Actually I am not quite sure about this, this is what I see from
> > > > ModelSim & VHDLSimli
> > >