rising_edge(clk) vs. (clk'event and clk='1')
Peter Sommerfeld
Are these two identical in all respects?
VhdlCohen
>rising_edge(clk) vs. (clk'event and clk='1')
>
>Are these two identical in all respects?
>
The function checks that the last value IS a '0', and does conversion to '1',
thus an 'H' is interpreted as '1'.
FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND (To_X01(s) = '1') AND
(To_X01(s'LAST_VALUE) = '0'));
in (clk'event and clk='1'), you get an edge if clk goes from 'X' to '1'. \Also
you get no edge if clk goes from '0' to 'H'.
For synthesis though, the synthesizer assumes a good clock that toggles between
'0' and '1'.
.. no funny stuff...
---------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdl...@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
---------------------
Clyde R. Shappee
If one is modeling an open drain driver (like an interrupt pin) and in the test
bench you drive the pin with an 'H' (to act as the pullup) and you test for a
rising edge, it will fail.
I have been there and done that. The function misses the transition to 'H'.
Clyde
Jonathan Bromley
<csha...@ieee.org> wrote:
>This [Ben's] is an important reply!
And not only in the context of clock edge detection.
>If one is modeling an open drain driver (like an interrupt pin) and in the test
>bench you drive the pin with an 'H' (to act as the pullup) and you test for a
>rising edge, it will fail.
>
>I have been there and done that. The function misses the transition to 'H'.
Me too. This problem often arises when you try to model chip-to-chip
interconnects in your VHDL test bench.
Consider using the TO_X01() strength-stripper function
(in std_logic_1164) as part of your input-pin model. It
will be ignored by synthesis.
Alternatively, make sure that the input signal hits a VHDL logic
operator such as "and" or "not", rather than an equality test. The
std_(u)logic operators handle H and L values correctly.
--
Jonathan Bromley
VhdlCohen
>
>Me too. This problem often arises when you try to model chip-to-chip
>interconnects in your VHDL test bench.
>
>Consider using the TO_X01() strength-stripper function
>(in std_logic_1164) as part of your input-pin model. It
>will be ignored by synthesis.
>
>Alternatively, make sure that the input signal hits a VHDL logic
>operator such as "and" or "not", rather than an equality test. The
>std_(u)logic operators handle H and L values correctly.
>--
Another alternative is to put the TO_X01 function in the port association list,
instead of the synthesizable model. I prefer that method.
thus,
port map (weak_hi_input => TO_X01(weak_hi_signal),
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdl...@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------
Jerry
> rising_edge(clk) vs. (clk'event and clk='1')
>
> Are these two identical in all respects?
for simulation. But there is one more reason to use
rising_edge and falling_edge - Cliff Cummings, well known
VHDL hater, is always using (CLK'event and CLK='1')...