How to Display std_logic_vector Value?

[Hon-Chi Ng]

Hi

How can I display the value of std_logic_vector?

I tried the followings using both Mentor's ModelSim and Synopsys's
Scirocco compiler, and none of them work.

a) Both compilers complain data_out is incorrect type for REPORT.
SIGNAL data_out : std_logic_vector(15 DOWNTO 0);
Check: PROCESS (data_out) IS BEGIN
REPORT "data_out = " & data_out;
END PROCESS Check;

b) Both compilers complain data_out does NOT have IMAGE attribute.
SIGNAL data_out : std_logic_vector(15 DOWNTO 0);
Check: PROCESS (data_out) IS BEGIN
REPORT "data_out = " & data_out'IMAGE;
END PROCESS Check;

I also looked up
http://www.vhdl.org/comp.lang.vhdl/FAQ1.html
but I couldn't find the solution for it.

Thanks. I appreciate your help.

Regards
Hon-Chi

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[Srinivasan Venkataramanan]

Hi,

Hon-Chi Ng wrote:
>
> Hi
>
> How can I display the value of std_logic_vector?
>
>

> a) Both compilers complain data_out is incorrect type for REPORT.
> SIGNAL data_out : std_logic_vector(15 DOWNTO 0);
> Check: PROCESS (data_out) IS BEGIN
> REPORT "data_out = " & data_out;
> END PROCESS Check;
>

data_out is std_logic_vector data type and REPORT can only "report"
STRING data type. So you should convert this std_logic_vector to a
string before passing onto REPORT.

One way of doing this could be to use the IMAGE attribute - BUT
IMAGE is defined *ONLY* for scalar data types.

So a feasible solution would be to use the IMAGE package from Ben
Cohen's web site, visit:

http://members.aol.com/vhdlcohen/vhdl/Models.html

>
> I also looked up
> http://www.vhdl.org/comp.lang.vhdl/FAQ1.html
> but I couldn't find the solution for it.
>

Well, Edwin (FAQ maintainer) - could you please update the FAQ with
this useful information? TIA

HTH,
Srini

--
Srinivasan Venkataramanan (Srini)
ASIC Design Engineer,
Chennai (Madras), India

[Ray Andraka]

The image attribute needs a scalar, so it won't work with a std_logic_vector.
Convert it to an integer using the
to_integer function in numeric.std.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email r...@andraka.com
http://www.andraka.com or http://www.fpga-guru.com

[pin...@my-deja.com]

You may want use this function:

-- By PK debug mean for printing std_logic
function prtstd( v : std_logic_vector ) return integer is
variable s : string( 3 downto 1 );
variable r : string( (v'left+1) downto (v'right+1) );
begin
for i in v'left downto v'right loop
--report std_logic'image(v(i));
s := std_logic'image(v(i));
--string must start/stop at 1
-- '1' we need only the second character
r(i+1) := s(2);
end loop;
report "dbg by pk " & r & " dbg end";
return 0;
end prtstd;

Call it by:
junk := prtstd( FileDesc.CurrentWord );

In article <940isc$qfe$1...@nnrp1.deja.com>,

[yaohan]

will it be possible to do the same thing in Altera Max+plus II program. ?
I mean to display value of std_logic_vector. ?

"Hon-Chi Ng" <honc...@my-deja.com> wrote in message
news:940isc$qfe$1...@nnrp1.deja.com...

[Srinivasan Venkataramanan]

Hi,

yaohan wrote:
>
> will it be possible to do the same thing in Altera Max+plus II program. ?
> I mean to display value of std_logic_vector. ?
>

If Max-plus II can "compile" the image pakage mentioned in my
earlier post YES!!

See: (http://members.aol.com/vhdlcohen/vhdl/Models.html)