advanced vhdl testbenches

[hulsk]

hi.

Hope to gather opinions & suggestions from VHDL experts on what is
most efficient way in learning how to create complex FPGA/ASIC
testbenches.

I've been self-learning VHDL for a year. Before moving into FPGA
synthesis, i would like to master the design test verification skills.

Bought the book:"Witing Testbenches" by Janick. However, sample VHDL
coding is incomplete and could not see the whole pictures.

Has anyone attended the DOULOS's expert VHDL course? If yes, how
helpful is it for a FPGA verification engineer.

thanks

;-)
hulsk

[Mike Treseler]

hulsk wrote:

> what is the most efficient way in learning

> how to create complex FPGA/ASIC testbenches.

Practice, practice, practice.

1. Read http://www.vhdl.org/comp.lang.vhdl/FAQ1.html
2. Get a good simulator and editor.
3. Start with a simple example design and testbench.
4. Add stuff to it, break it, fix it. Repeat.
5. Read Ashenden and try out an example of everything for yourself.

--Mike Treseler

[VhdlCohen]

>> what is the most efficient way in learning
>> how to create complex FPGA/ASIC testbenches.

My site has examples of transaction-based TB. In addition my last 2 books
provide complete examples.
en Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdl...@aol.com
Author of following textbooks:
* Component Design by Example ... a Step-by-Step Process Using
VHDL with UART as Vehicle", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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[Stefan Doll]

> Hope to gather opinions & suggestions from VHDL experts on what is
> most efficient way in learning how to create complex FPGA/ASIC
> testbenches.

Seems like a good opportunity to push my website:
http://www.i2.i-2000.com/~stefan/vcourse/html/index.html

It's an online VHDL verification course.

It's free, have a look. :)

Cheers

Stefan

[hulsk]

Thank you so much for your wonderful tips on learning! Complex VHDL
testbench can be quite terrifying -- file I/O, monitor, assertion
checking,...!

Been with a company, working on FPGA design test verification suite.

I guess my major concern is how to verify a design and what test
stimuli to apply for fully exercising the DUT under simulation. How
do we know the job is done? Situation can be some time annoying!

From my personal point of view, it becomes extremely handy to know
what appropriate test coverage should be performed.

Could anyone comment on the usefulness of "Principles of Verifiable
RTL design -2nd ed." for VHDL design verification engineers. I know
nothing about Verilog construct. However, the 'table of content' of
this book appears to be quite relevant to design verification
engineers, apart from ASIC/FPGA design engineers.

Found an article from LATTICE SEMI, "Behavioural modellings in VHDL
simulation" by Gary Peyrot. I have quite yet finished with this
article, but the first few pages seems to be "educating" for junior
engineer, fresh out of university like me.

Once again, thank you for your contribution on this subject. Do not
hesitate to contribute/share your experience if you want to! :-)

cheerio,
hulsk

ste...@i-2000.com (Stefan Doll) wrote in message news:<976df3a6.01110...@posting.google.com>...

[Colin Marquardt]

huls...@yahoo.com (hulsk) writes:

> Found an article from LATTICE SEMI, "Behavioural modellings in VHDL
> simulation" by Gary Peyrot. I have quite yet finished with this
> article, but the first few pages seems to be "educating" for junior
> engineer, fresh out of university like me.

For the rest of the group: to get this, either go to http://www.vantis.com
and search for "CP001", or try looking for "Behavioral Modeling in VHDL
Simulations" in Google.

Colin