what is the difference between Aggregate and Concatenation?

l...@bd748.pku.edu.cn

unread,

Mar 8, 1998, 3:00:00 AM3/8/98

to

Hi, i'm confused about the difference between Aggregate and Concatenation
operation in VHDL,these two operation can combine bits of operators,for
example: vec:STD_LOGIC_VECTOR(2 downto 0); a,b,c:STD_LOGIC; ......
(a,b,c)<=vec; vec<=a&b&c;

but
vec<=(a,b,c);
a&b&c<=vec;
seems to be a invalid express,can anybody explain why?
Any help will be appreciated!

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/ Now offering spam-free web-based newsreading

Stefan Doll

unread,

Mar 9, 1998, 3:00:00 AM3/9/98

to

l...@bd748.pku.edu.cn wrote:

>Hi, i'm confused about the difference between Aggregate and Concatenation
>operation in VHDL,these two operation can combine bits of operators,for
>example: vec:STD_LOGIC_VECTOR(2 downto 0); a,b,c:STD_LOGIC; ......
>(a,b,c)<=vec; vec<=a&b&c;

> but
> vec<=(a,b,c);
> a&b&c<=vec;
> seems to be a invalid express,can anybody explain why?
> Any help will be appreciated!

Well, basically "&" is an operator, so it belongs on the right hand
side of an assignment. To put it on the left side is a bit like
writing "a+b <= 7;".

I think aggregate should work on both sides of the equation.
(It does with my simulator at least.)

Hope that helps

Stefan

Andreas Gieriet

unread,

Mar 10, 1998, 3:00:00 AM3/10/98

to l...@bd748.pku.edu.cn

l...@bd748.pku.edu.cn wrote:
>
> Hi, i'm confused about the difference between Aggregate and
> Concatenation
> operation in VHDL,these two operation can combine bits of
> operators,for example:
> vec:STD_LOGIC_VECTOR(2 downto 0); a,b,c:STD_LOGIC; ......
> (a,b,c)<=vec; vec<=a&b&c;
>
> but
> vec<=(a,b,c);
> a&b&c<=vec;
> seems to be a invalid express,can anybody explain why?
> Any help will be appreciated!
>

Let's start with the simpler one: the concatenation.
The concatenation is an *operator*. Since it is an operator, it can be
*overloaded* and *not* used as left-hand expression.
E.g., neither a&b<=c; nor a+b<=c; is legal vhdl code.

The aggregate instead is *not* an operator. An aggregate expression
is allowed as left-hand expression (like a name), as long as all
elements of the aggregate are legal left-hand expressions (e.g., names).
E.g., (a,b)<=c; is legal vhdl code.

Furthermore, an aggregate is the only way to assign a record's value
in one expression (where as the array has the alternative of the "&"
operator if it is defined for that type and it is unique in the given
context).

--
Andreas Gieriet

(Please replace "nospam" by "pobox" in the return address,
which has been altered to foil junk mail senders)

Paul J. Menchini

unread,

Mar 10, 1998, 3:00:00 AM3/10/98

to

Andreas Gieriet (an...@nospam.ch) wrote:

: l...@bd748.pku.edu.cn wrote:
: > Hi, i'm confused about the difference between Aggregate and
: > Concatenation
: > operation in VHDL,these two operation can combine bits of
: > operators,for example:
: > vec:STD_LOGIC_VECTOR(2 downto 0); a,b,c:STD_LOGIC; ......
: > (a,b,c)<=vec; vec<=a&b&c;
: >
: > but
: > vec<=(a,b,c);
: > a&b&c<=vec;
: > seems to be a invalid express,can anybody explain why?
: > Any help will be appreciated!
: >

: Let's start with the simpler one: the concatenation.
: The concatenation is an *operator*. Since it is an operator, it can be
: *overloaded* and *not* used as left-hand expression.
: E.g., neither a&b<=c; nor a+b<=c; is legal vhdl code.

: The aggregate instead is *not* an operator. An aggregate expression
: is allowed as left-hand expression (like a name), as long as all
: elements of the aggregate are legal left-hand expressions (e.g., names).
: E.g., (a,b)<=c; is legal vhdl code.

Well, to be precise, the aggregate is allowed as a target only because the
LRM makes special provisions to have targets *in the form of* aggregates--
the targets are not really aggregates.

Moreover, the restrictions are more comprehensive than stated. In particular,
the aggregate elements must be locally static names (so the analyzer can
perform coverage analysis).

Paul