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record and alias: do they work together

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Michael Caffrey

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Jun 17, 1998, 3:00:00 AM6/17/98

Hello,
I am trying to model a bus and have a question or two: I want to do
something like this...
but first, are multimode records out of the question? It looks like
they are, but I ask because they would be so useful....

architecture behave of rca_board is
type lcl_vme_bus is record
Addr_Valid : STD_LOGIC_VECTOR(5 downto 0);
lcl_RSTn : STD_LOGIC_VECTOR(5 downto 0);
lcl_IACKOUT : STD_LOGIC_VECTOR(5 downto 0);
R_P : STD_LOGIC;
W_P : STD_LOGIC;
end record;

type lcl_v_bus_i is record
Addr_Valid : STD_LOGIC;
RSTn : STD_LOGIC;
IACKn : STD_LOGIC;
r_p : STD_LOGIC;
w_p : STD_LOGIC;
end record;

signal board_bus : lcl_vme_bus;
signal device_bus : lcl_v_bus_i;
-- I know this syntax won't work, what is correct?
alias TEST : lcl_vme_bus is board_bus(
Addr_Valid(5),
lcl_RSTn(5),
lcl_IACKOUT(5),
R_P,
W_P);
begin
device_bus <= test;
.
.
.

Gracias!

Michael Caffrey
m...@lanl.gov

Paul J. Menchini

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Jun 17, 1998, 3:00:00 AM6/17/98

Michael Caffrey (m...@lanl.gov) wrote:
: I am trying to model a bus and have a question or two: I want to do

You can't use an alias to create a value out of bits and pieces of
different objects. An alias (as it's name hopefully implies) is used
to create multiple names for a "thing" (or a part of a "thing"). (In
VHDL'87, "thing" == "object", but "thing" has a much wider meaning in
VHDL'93.)

If I understand correctly what you're trying to do, it's quite simple:

device_bus <= (Addr_Valid(5), lcl_RSTn(5), lcl_IACKOUT(5), R_P, W_P);

i.e., use an aggregate to construct the record value.

If you're willing to make lcl_v_bus_i an array type, you can still use
the aggregate, or you may use concatenation:

device_bus <= Addr_Valid(5) & lcl_RSTn(5) & lcl_IACKOUT(5) & R_P & W_P;

Hope this helps,

Paul

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