Generic multiplexer in VHDL
Johan Ditmar
I would like to implement a onehot multiplexer in VHDL, where both the width
of the inputs/output and the number of inputs are generics. With onehot
multiplexer, I mean that each input has its own enable signal and if an
enable signal is high, the input should be propagated to the output. The
thing that I have trouble with is the generic number of inputs, how can this
be implemented? Any help is appreciated.
Thank you,
Johan Ditmar
fred
length - nothing says the vector has to be binary. Slice the selects
outside.
That said, select(0 downto 0) is messy (but feasible).
Best,
Fred
Johan Ditmar <johan....@nospam.celoxica.com> wrote in message
news:3b7cd7e9$1...@news.star.co.uk...
Jerry
Johan,
Look at this code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity genmux is
generic ( width : positive := 8 );
port (
Din, Sel : in std_logic_vector( width-1 downto 0);
Dout : out std_logic
);
end genmux;
architecture gener of genmux is
begin
mx: for i in Din'range generate
Dout <= Din(i) when Sel(i)='1' else 'Z';
end generate mx;
end gener;
architecture beh of genmux is
begin
process (Din, Sel)
variable tmp : std_logic;
begin
tmp := '0';
for i in Din'range loop
tmp := tmp or (Din(i) and Sel(i));
end loop;
Dout <= tmp;
end process;
end beh;
-- #### END OF CODE ####
The first architecture (gener) is using genrate statement
to implement one tristate buffer per each bit of your mux.
Perfect if your target architecture can handle tristates
and it's OK with you to implement mux this way.
The second architecture (beh) uses loop statement to suggest
'sum-of-products' combinatorial implementation.
Good solution if there are no tristates in your target
architecture and/or you prefer pure combinatorail approach.
Of course this version uses more area.
I have checked both using Synplify Pro and both were implemented
as expected.
Hope it helps,
Jerry