How to use "black box" RAM model in Design Compiler?
Tuukka Toivonen
Compiler synthesis tool?
I'm writing a synthesizable VHDL model, which uses RAM of few kilobytes.
Design Compiler can synthesize RAMs only as flip flops, and this size is too
big for that. So, I need to tell it to treat an entity as block box and
prevent it from synthesizing the RAM.
I tried doing this by wrapping the "architecture" part of my RAM model
inside --pragma synthesis_off/on pair, but then Synopsys complains:
'SYNC_SRAM' was not identified as a synthetic library module
and could not be successfully elaborated from design library 'WORK'
Any idea?
Tuukka Toivonen
> I'm writing a synthesizable VHDL model, which uses RAM of few kilobytes.
> Design Compiler can synthesize RAMs only as flip flops, and this size is too
> big for that. So, I need to tell it to treat an entity as block box and
> prevent it from synthesizing the RAM.
>
> I tried doing this by wrapping the "architecture" part of my RAM model
> inside --pragma synthesis_off/on pair, but then Synopsys complains:
> 'SYNC_SRAM' was not identified as a synthetic library module
> and could not be successfully elaborated from design library 'WORK'
Too bad, nobody seems able to help. Let's make an easier question: can I
just ignore this error? It seems to produce sane results nevertheless
(although the popup-dialog that always appears is irritating).
And also: how big area a RAM macroblock, say 1024*25 bits or something like
that, would take? (compared to NANDs, for example)
Should I learn using Synopsys Library Compiler and make a library model of
the RAM to avoid the error message shown above?
VhdlCohen
One option is to use Synopsys Design Ware, but make sure you have a license for
the components that you need.
Below is from DW documention CD.
library IEEE,DW06,SYNOPSYS,DWARE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use DW06.DW06_components.all;
use SYNOPSYS.ATTRIBUTES.all;
use DWARE.Dwpackages.all;
entity DW_ram_r_w_s_dff_bc is
generic(data_width : INTEGER:=10; depth : INTEGER:=8);
port( rst_n,clk : in std_logic ;
rd_addr : in std_logic_vector(bit_width(depth)–1 downto 0);
wr_addr : in std_logic_vector(bit_width(depth)–1 downto 0);
data_in : in std_logic_vector(data_width–1 downto 0);
data_out : out std_logic_vector(data_width–1 downto 0));
end DW_ram_r_w_s_dff_bc;
A model of the architecture of the ram is in their CD, and can be used for
simulation purposes.
To use the ram:
library IEEE,DWARE,DW06;
use IEEE.std_logic_1164.all;
use DWARE.DWpackages.all;
use DW06.DW06_components.all;
entity DW_ram_r_w_s_dff_inst is
generic (
inst_data_width : INTEGER := 8;
inst_depth : INTEGER := 8;
inst_rst_mode : INTEGER := 0
);
port (
inst_clk : in std_logic;
inst_rst_n : in std_logic;
inst_cs_n : in std_logic;
inst_wr_n : in std_logic;
inst_rd_addr : in std_logic_vector(bit_width(inst_depth)–1 downto 0);
inst_wr_addr : in std_logic_vector(bit_width(inst_depth)–1 downto 0);
inst_data_in : in std_logic_vector(inst_data_width–1 downto 0);
data_out_inst : out std_logic_vector(inst_data_width–1 downto 0)
);
end DW_ram_r_w_s_dff_inst;
architecture inst of DW_ram_r_w_s_dff_inst is
begin
–– Instance of DW_ram_r_w_s_dff
U1 : DW_ram_r_w_s_dff
generic map ( data_width => inst_data_width, depth => inst_depth, rst_mode
=> inst_rst_mode )
port map ( clk => inst_clk, rst_n => inst_rst_n, cs_n => inst_cs_n, wr_n
=> inst_wr_n, rd_addr => inst_rd_addr, wr_addr => inst_wr_addr, data_in =>
inst_data_in, data_out => data_out_inst );
end inst;
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdl...@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------
Tuukka Toivonen
>>> I'm writing a synthesizable VHDL model, which uses RAM of few kilobytes.
>>> Design Compiler can synthesize RAMs only as flip flops, and this size is
>>too
>>> big for that. So, I need to tell it to treat an entity as block box and
>>> prevent it from synthesizing the RAM.
> One option is to use Synopsys Design Ware, but make sure you have a license for
...
> A model of the architecture of the ram is in their CD, and can be used for
> simulation purposes.
Thanks--but as the same documentation says, the RAM size should be less than
256 bits, 100 times less than I need. And the very problem was with
synthesis, not with simulation. Not necessarily synthesizing the RAM itself,
but at least the architecture, which instantiates the RAM.
I tried the following:
entity MY_RAM
...
end;
--pragma translate_off
architecture MY_RAM
...
end;
--pragma translate_on
However, this made the synthesis tool complain loudly about the missing
architecture. I got an advice (via private mail--thanks) to use instead:
entity MY_RAM
...
end;
architecture MY_RAM
--pragma translate_off
...
--pragma translate_on
end;
I.e. I give the architecture block to the synthesis tool, but leave it
empty. I suppose I now get some usable synthesis results. At least the tool
doesn't complain anymore.
VhdlCohen
>
> entity MY_RAM
> ...
> end;
> architecture MY_RAM
> --pragma translate_off
> ...
> --pragma translate_on
> end;
>
>I.e. I give the architecture block to the synthesis tool, but leave it
>empty. I suppose I now get some usable synthesis results. At least the tool
>doesn't complain anymore.
But the sysnthesis tool will NOT instantiate a RAM model. So your design is
without RAM, and any connections to your RAM will be optimized out.
This is not a solution for you. You need to get the right DW ram, or library
of ram from your target library vendor (e.g., LSI if that is your target).
Tom Verbeure
You should create a component of your RAM and this component and the code
that uses it. Don't analyze the entity and architecture of the RAM itself.
This should allow you to elaborate your design, even though synopsys will
give a warning about not being able to find a model for the RAM... You can
then synthesize, but obviously without taking timing condition into account
of the RAM interface.
To make it really clean (read: no warnings during elaborate and
compilation), you need a synopsys .lib library model of the RAM. This .lib
model must be first converted into a .db file. Just use read_lib in
dc_shell. It will complain and give an error that you don't have library
compiler, but you can ignore this error: you can will write out the model
as a DB file. (The error is really about special .lib feature that you
don't need for a black box only model).
If you don't have a .lib of the RAM model, then you will have to make one.
Good luck: it is not that difficult, but it will cost you quite a lot of
time. :-]
Hope this helps (it has always worked for me...),
Tom
Tom Verbeure
As a follow-up to the answer of VhdlCohen:
the reason why you should not analyze the empty version of the architecture
of the RAM, is exactly to avoid that it will be optimized away.
If there is only a component and not entity/arch, then synopsys will
consider it to be a black box and the connections will remain. (Though it
will keep on complaining about the missing black box...)
Tom