Cypress Warp2 4.0; Anybody used it?
Chris Pruett
Apparently Cypress is offering Warp2 Release 4.0
for $99. It claims to support standard VHDL synthesis
and simulation. Of course it probably only synthesizes for Cypress
FPGA's or something but I don't care since I am thinking about
using it in a class.
Anybody used this beast? Is it any good? Is it useable for
a moderately complicated school project?
Thanks,
CP
--
What happens if a big asteroid hits Earth? Judging from realistic
simulations involving a sledge hammer and a common laboratory frog,
we can assume it will be pretty bad. - Dave Barry
Bert Cuzeau
Hello, (I am French, forgive my style & grammar)
Some VHDL tools are extremely cheap, and hence
often have excellent perf / price ratios.
HOWEVER, I would be careful before making the price
the first criterion for a tool to be used in VHDL courses.
(I use to say some of these tools are "dangerously good")
In France, a renowned teacher did that, and he
published a book and an article containing one
of the "classics" in VHDL synthesis errors,
namely the misuse of variables.
--A whole chapter in my VHDL training courses--.
You can get the story and the small source code
at my homepage as listed below, go to the
brain-teaser section.
The problem was that Warp (a version older than the
one you mention though) did incorrectly synthesize
his code. He could not spot his error because the
"simulator" in Warp was merely a non-causal
test-vector-based equation-simulator which chewed
the generated logic array + input vectors and gave
the output vectors (in a nice graphical display).
You should be also aware of another major
shortcoming of the functional-only approach :
students will not understand the glitches they
will have in their PLDs which simulated so nicely !
The only way to get convinced about design
issues is to use POST-LAYOUT timing simulation.
Eg : problems induced by poor design practices
like inconsiderate use of asynchronism....
I have tens of designs (most collected in the
industry, from customers) which simulate fine
but behave erratically in the chips...
When teaching/learning something as delicate as
VHDL, my opinion is that you need an absolutely
_perfect_ BEHAVIOURAL simulator interpreting
_directly_ your source code in total compliance
with the rules edicted in the LRM.
Eg : teaching scheduling is so much easier.
And you need accurate post-route timing simulation
to detect violations & glitches in the synthesized part.
Anything less seems dangerous to me.
In France, we do install a lot of Synario systems also
in Engineering Schools, and all took "our" VHDL
simulator (the one which Synario integrates : namely
Model Tech's V-System).
You might also consider Accolade's simulator.
(http://www.acc-eda.com)
If you validate your code with a good simulator,
then using Warp to fit the lab exercises in PLDs
could be acceptable, but once again, you won't
demonstrate design errors induced by implementation.
Teachers do like Synario because everything (including
the design flow) is so transparently integrated and
painless to use, that courses may entirely focus on
the real issues rather than the tools !
Last but not least, writing structural VHDL and pages
of declarations is a chore -it's my opinion- !!!
Who does write manually PCB netlists ?
To me, a schematic capture is the right approach
to Top-Down design. Pages of structural VHDL are not.
That's also why I love VHDL in the Synario flow,
I never write manually a test-bench template, nor
the VHDL declarations...
Again, all the above are only personal opinions.
Hope it helps,
Regards,
--
//////////////////////////////////////////////////////
Bert CUZEAU - ALSE France
* FPGA-CPLD Design and Synario Expert
* VHDL and Synario Trainings
* Consultant
http://ourworld.compuserve.com/homepages/alse
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Chris Pruett <cpr...@ionet.net> wrote in article
<cpruett-ya0240800...@news.ionet.net>...
pchaffey
Bert Cuzeau wrote:
>
> Hello, (I am French, forgive my style & grammar)
<CUT>
> Last but not least, writing structural VHDL and pages
> of declarations is a chore -it's my opinion- !!!
> Who does write manually PCB netlists ?
> To me, a schematic capture is the right approach
> to Top-Down design. Pages of structural VHDL are not.
> That's also why I love VHDL in the Synario flow,
> I never write manually a test-bench template, nor
> the VHDL declarations...
>
I agree....
I have seen the Synario software demonstrated and the schematic
capture looks to do the structural description very well. Just
for the record there is a standalone tool called EASE from
Translogic that does the schematic structural VHDL description
well also. This tool also has the feature of graphical state
machine entree which is very nice.
Paul Chaffey.
_/_/_/_/ _/ _/ _/_/_/_/ Paul Chaffey C.Eng M.I.E.E
_/ _/ _/_/ _/_/ _/ Philips Medical Systems Nederland
_/_/_/_/ _/ _/ _/ _/ Internet(W): pcha...@best.ms.philips.com
_/ _/ _/ _/ Internet(H): 10155...@compuserve.com
_/ _/ _/ _/_/_/_/ Tel: +31 40 2762344
Hans Tiggeler
I have been playing with it for the past few weeks and so far in term of price
performance ratio I think it is near perfect!
There are a few "features" which could be improved, but what do you expect for
32 pounds. I bought the compiler for the same reason as you did, i.e. for
small student projects. You can buy a parallel download cable (69 pounds)
which will allows you to download the design into Cypress ISR devices. This is
ideal for "trial and error" based projects. Unfortunately I haven't used this
cable yet because I am still waiting for the actual devices :-(
Hans.
In article <cpruett-ya0240800...@news.ionet.net>,
cpr...@ionet.net says...
haw...@hiwaay.net
In article <5bvqi9$r...@info-server.surrey.ac.uk>, ees...@ee.surrey.ac.uk
says...
with reasonable success. The simulator is okay, not good for lengthy runs or
complex analysis - better to build a test bench. The logic synthesis is good,
with plenty of detailed information concerning how it implemented your code.
The WARP environment only works with Cypress parts (or crosses to Cypress),
and covers the spectrum (from 22V10 up through FPGA) of programmable logic. I
am currently using version 4.0 under Windows95 which allows you to build
projects, etc.. Not too bad for the pricem, the VHDL design environment for
$99US is exceptional. No, I do not have any affiliation with Cypress ;).
My applications have ranged from a state machines to simple structural
implementations of MSI/LSI logic into single chips. I've used the CY7C372 and
CY7C374i (ISP) parts up to 50 MHz without failure. The in-system parts are
HARD to get, but not the kit. The first ISP parts I used were samples, but now
it appears that Cypress is getting their act together and starting to ship
silicon. My end products are typically laboratory instruments built for the
U.S. Army Missile Command on Redstone Arsenal (Huntsville, AL) at their
McMorrow Labs facility (birthplace of Patriot/Javelin/Hellfire/Redstone/
Minuteman/etc/etc)...
Any more info email me at eric.t....@cpmx.saic.com.
Richard Schwarz
The Cypress partsa nd compiler are great, but for real FPGA designs,
XILINX is the way to go. The start up costs have typically been high,
but now at APS you can get a complete ISA test board/synthesis/logic
simulator/router for as lows as $650.00! See: