case statement concatenation condition

[Mark]

One syntax I've favored in verilog for compactness (and to see that
all variable conditions are covered) is to express logic in a truth
table as:

casez( {a,b,c} )
3'b000: z <= ...
3'b001: z <= ...

I'm trying to use a similar style in VHDL, and am wondering if there
is an elegant way to do this. My first attempt was:

case a & b & c is
when "000" => z <= ...
when "001" => z <= ..

With the error, "Ambiguous type in infix expression; unsigned or
signed."

OK. Strong typing... doesn't know what type the concatenation should
resolve to... so I write:

case std_logic_vector'(a & b & c) is
when "000" => z <= ...
when "001" => z <= ..

I get the model sim warning "Array type case expression must be of a
locally static subtype."

I could assign the concatenation first to a variable (verbose), or I
could disabled the warning in modelsim (but it does seem to be a valid
violation of the VHDL language), but does anyone have a suggestion on
how to write this in both a terse and correct way?

Thanks,

Mark

[Jonathan Bromley]

On Wed, 10 Jun 2009 08:01:17 -0700 (PDT), Mark wrote:

>One syntax I've favored in verilog for compactness (and to see that
>all variable conditions are covered) is to express logic in a truth
>table as:
>
>casez( {a,b,c} )
> 3'b000: z <= ...
> 3'b001: z <= ...
>
>I'm trying to use a similar style in VHDL, and am wondering if there
>is an elegant way to do this. My first attempt was:
>
>case a & b & c is
> when "000" => z <= ...
> when "001" => z <= ..
>
>With the error, "Ambiguous type in infix expression; unsigned or
>signed."
>
>OK. Strong typing... doesn't know what type the concatenation should
>resolve to... so I write:
>
>case std_logic_vector'(a & b & c) is

You need to be even stronger... the *subtype* of the
case expressions is still not "locally static". And
yes, it's a pain and everyone agrees it's a pain. It
just falls out of the language rules like that.

Luckily there's a relatively simple fix. Declare
a subtype of std_logic_vector (typically in the
declarative region of your process):

subtype slv3 is std_logic_vector(2 downto 0);

And then you can qualify the case expression with
the locally-static subtype:

case slv3'(a & b & c) is
when "000" => ...

and all will be well.

Of course, you may well need rather a lot of such
subtype declarations, if you have numerous different
case statements.

Enjoy :-)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

[Mark]

On Jun 10, 10:11 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

>
> The contents of this message may contain personal views which

> are not the views of Doulos Ltd., unless specifically stated.- Hide quoted text -
>
> - Show quoted text -

Jonathan,

Thanks! Like that much better than the alternatives I was considering.

Mark

[Matthew Hicks]

> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan...@MYCOMPANY.com http://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which are not
> the views of Doulos Ltd., unless specifically stated.
>

You may not even need to create a named subtype for this. You can create
an anonymous subtype of the range you need. I have tried to write this up
in a case statement, but I have done similar things in type declarations.

i.e.: case std_logic_vector(2 downto 0)'(a & b & c) is...

---Matthew Hicks

[Jonathan Bromley]

On Wed, 10 Jun 2009 17:47:04 +0000 (UTC), Matthew Hicks wrote:

>You may not even need to create a named subtype for this. You can create
>an anonymous subtype of the range you need. I have tried to write this up
>in a case statement, but I have done similar things in type declarations.
>
>i.e.: case std_logic_vector(2 downto 0)'(a & b & c) is...

I can imagine that some tools may tolerate this, but
it does not appear to be legal VHDL. The syntax of
a qualified expression is

type_mark'(expression)

and a type_mark must be simply a type name or subtype
name. A "subtype indication" won't do.
--
Jonathan Bromley, Consultant

[Matthew Hicks]

> On Wed, 10 Jun 2009 17:47:04 +0000 (UTC), Matthew Hicks wrote:
>
>> You may not even need to create a named subtype for this. You can
>> create an anonymous subtype of the range you need. I have tried to
>> write this up in a case statement, but I have done similar things in
>> type declarations.
>>
>> i.e.: case std_logic_vector(2 downto 0)'(a & b & c) is...
>>
> I can imagine that some tools may tolerate this, but it does not
> appear to be legal VHDL. The syntax of a qualified expression is
>
> type_mark'(expression)
>
> and a type_mark must be simply a type name or subtype name. A
> "subtype indication" won't do.
>

> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan...@MYCOMPANY.com http://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which are not
> the views of Doulos Ltd., unless specifically stated.
>

You are right, I took a quick glance at the LRM, saw that it took an expression
and figured a subtype indication (which consists of a type_mark and a possible
constraint) would work. It doesn't since, as you pointed out, a qualified
expression is limited to type marks.

---Matthew Hicks