Delay in a CPLD with VHDL
TigerMole
lets say 500 ns.
Here is what i tried, but it did't work in the CPLD.
CE <= not CE after 500 NS;
sorry, i am a newbie, can anybody help me ?
Or are delays not possible in CPLDs ?
TIA
TigeMole
Uwe Bonnes
: I would like to generate a fixed delay ...
: lets say 500 ns.
Always think how the hardware should syntesize your code. How can a delay be
implemented? Not alone with logic alone.
Either generate the delay external with e.g. a monoflop, or use a counter,
that you start and that counts clock pulses until 500 ns are over.
Bye
--
Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
TigerMole
<b...@elektron.ikp.physik.tu-darmstadt.de> wrote:
>TigerMole <Mo...@huegel.de> wrote:
>: I would like to generate a fixed delay ...
>: lets say 500 ns.
>
>: Here is what i tried, but it did't work in the CPLD.
>
>: CE <= not CE after 500 NS;
>
>: sorry, i am a newbie, can anybody help me ?
>
>: Or are delays not possible in CPLDs ?
>
>Always think how the hardware should syntesize your code. How can a delay be
>implemented? Not alone with logic alone.
I thought logic gate have a propagation delay ...
if i build a chain of gates ... could there be a delay then ?
>
>Either generate the delay external with e.g. a monoflop, or use a counter,
>that you start and that counts clock pulses until 500 ns are over.
I really wanted to avoid any external elements, i don't have enough
space.
Uwe Bonnes
...
:>: Or are delays not possible in CPLDs ?
:>
:>Always think how the hardware should syntesize your code. How can a delay be
:>implemented? Not alone with logic alone.
: I thought logic gate have a propagation delay ...
: if i build a chain of gates ... could there be a delay then ?
Of course, there is a delay. However there are at least two drawbacks:
- the syntesis tools mostly will optimize away this chain of gates.
- the delay is highly unriliable, depending on temperture of the chip, and
will differ significantly from chip to chip.
:>
:>Either generate the delay external with e.g. a monoflop, or use a counter,
:>that you start and that counts clock pulses until 500 ns are over.
: I really wanted to avoid any external elements, i don't have enough
: space.
Then use the approach with counting clock pulses after your trigger event.
TigerMole
I will do the counting solution :-)
At least i can stop trying to do the delay without a clock now ...
I heard of a KEEP attribute which prevents the signals from
being optimized !? Can i use this ?
Unfortunately its not sure that i will have an external clock, so
i may be out of luck there, too ....
thx
Mole
Uwe Bonnes
...
: I will do the counting solution :-)
: At least i can stop trying to do the delay without a clock now ...
: I heard of a KEEP attribute which prevents the signals from
: being optimized !? Can i use this ?
You can use it, but most synthesis tools have their own living and a lot of
experimenting is needed to get the tool to accept the attribute ( at least
in my experience)
: Unfortunately its not sure that i will have an external clock, so
: i may be out of luck there, too ....
The 500 ns are a lot. Look at the internal delay of a CPLD, like the
XC95288XL-10. With a lot of fiffling you will reach a max delay of perhaps
10 ns per stage. For 500 ns you will need 50 stages, that is about 165 of
the total resources. If you don't have an external clock, consider an
external delay device, like the Dallas/Maxim ICs.
: On Wed, 22 Jan 2003 09:29:18 +0000 (UTC), Uwe Bonnes
: <b...@elektron.ikp.physik.tu-darmstadt.de> wrote:
:>TigerMole <Mo...@huegel.de> wrote:
:>...
:>:>: Or are delays not possible in CPLDs ?
:>:>
Please,
use a modest quoting style: Quote only needed parts at the top, put your
comments below and edit away unneded parts of what you quote.
TigerMole
Thanks again.
TigerMole